This is a logic analyzer add-on for the TI MSP430 Launchpad. It is inspired by the Logic Shrimp - you could say it is a rip off the design - that would be quite fair.
The prototype is built on perf board with soldered point to point wiring.
The first test was done with a 74HC4040 counter clocked by a 10 MHz canned oscillator.
The FTDI BOB shown is optional. The VCP on the launchpad can be used but it is limited to 9600 bps, so rather slow.
The max sample rate is 16 Msps. The top trace is 5 MHz and the jitter is clearly visible.
A custom config file for OLS was made to support the specific feature set of the hardware and current firmware.
There are a few differences in the design compared to the Logic Shrimp.
The SPI RAM chips have the SI and SO lines tied together. This reduces the pin count needed on the microcontroller. The SO line is tristate whenever the data is being sent so there is no bus conflict. The firmware must be careful to properly track the read/write state and set it's port direction appropriately.
The MSP430 can output it's internal clock on P1.4, so this is used to clock the SPI RAM during acquisition. This feature eliminates the need for a tristate buffer between the oscillator and RAM CLK line. The internal oscillator of the MSP430 is used so there is no osc module or xtal needed. The sample rate can be adjusted by changing the internal clock frequency and clock dividers. The current firmware uses the precalibrated 1 and 16 MHz clock frequencies and dividers of 1, 2, 4 and 8 for sample rates of 16, 8, 4, 2, 1, 0.5, 0.25, 0.125 Msps. The internal osc of the MSP430 is very versatile so more sample rates can be added in future firmware.
There is an optional phase shift R/C on the latch clock to ensure data hold time for the RAM. This is not on the prototype and so far it seems to work fine without it.
A PCB has been designed, but none made yet. It is 50 mm x 50 mm for low cost.Firmware and Eagle CAD files