Power supply using a 2U rack chassis (56K warning)

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Re: Power supply using a 2U rack chassis (56K warning)

Postby rsdio » Wed Aug 31, 2011 3:54 am

hak8or wrote:Here is what the inside of it looks like. There was another board ontop that also had more FPGA's, but I took it out a long time ago to try to get access to the JTAG pins. It is rather heavy, and I will tell you why later. I will say now though, it was a major surprise!

I did not ever see a followup to this teaser. Why was the top board heavy? What was the major surprise?
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Re: Power supply using a 2U rack chassis (56K warning)

Postby bearmos » Wed Aug 31, 2011 6:28 am

rsdio wrote:Why was the top board heavy? What was the major surprise?

There was something like a 1/2" aluminum face plate on the front of the rack ( i think ). it was in one of the pictures.
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Re: Power supply using a 2U rack chassis (56K warning)

Postby hak8or » Wed Aug 31, 2011 10:05 am

rsdio wrote:
hak8or wrote:Here is what the inside of it looks like. There was another board ontop that also had more FPGA's, but I took it out a long time ago to try to get access to the JTAG pins. It is rather heavy, and I will tell you why later. I will say now though, it was a major surprise!

I did not ever see a followup to this teaser. Why was the top board heavy? What was the major surprise?

Sorry, I think my wording was not too good. I was referring to the entire unit when I said "it is rather heavy", not the top PCB. If you want though, I would be more than happy to upload some pictures of the top pcb.

Yeah, the front plate was a thick slab of metal, hence being so heavy. It was surprising since I never saw such a usage of metal. Normally companies make it look heavy and very durable, but have a empty body in effort to use less metal which saves them money, but in this situation they went all out and just stuck a large slab of aluminum to the front.

Currently this project is progressing very slowly. I was hoping to have a majority of this done before college, but it turns out that I wanted more out of this, which uses up even more time. Some additions I am using for this are a 50 MSPS ADC which I will use as current measurement and a low spec oscilloscope, a CPLD for working with transferring the data from ADC to SRAM and act as a clock controller for the high speed adc, a 18 bit ADC as a very precise current/voltage monitor (3.75 SPS, heh), and I might maybe switch away from the PIC32 and instead to another micro controller due to Ian's latest post.

I was looking at the Renesas RX since it supports a full fledged opensource suite, and I have the RDK for testing code. From what I see, they have the eclipse IDE and a proper GCC tool chain for the RX, but the programmer is fully closed source. I also had nothing but bad experiences with the eclipse environment for the RX. Last time I tried to use the opensource tools for the Renesas RX MCU, all the documentation was just thrown around everywhere, and apparently to program the RX from eclipse, I had to save the project, export it to the HEW ide, open the Hew IDE, and then program through the HEW IDE, which seems ridiculous. Also, the HEW ide is closed source from what I remember. Programming the RX mcu might also be a problem, but I remember something about booting from a SPI flash by setting a mode using the pins on the RX mcu, but I cannot find anything about that.

I would consider the avrgcc tool chain, but all the AVR's out there go no faster than 20 MHz?
Are there any high speed MCU's that are also properly opensource?
I want to learn other mcu's, the RX mcu from renesas seems awesome, but the way that the documentation is thrown around, and what seems to be no proper support for the eclipse IDE, and what seems to me as a very confusing process to program the chip with open source tools, I will probably just stick with the pic32.I just need to check what PIC32 chips I can program using the Pickit2. :P

Also, this project will go along a bit slowly, since I just started college and my schedule kind of sucks, which results in me having to stay on campus for nearly four hours doing nothing between classes. At least I have all the software for designing this project on my laptop. I will see about uploading a schematic of what I have so far.
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Re: Power supply using a 2U rack chassis (56K warning)

Postby hak8or » Sun Sep 04, 2011 11:12 pm

Hello there everyone!

Been a while, and I have realized that as of now, with college I have lost a very large amount of my free time. I am still rethinking a lot, and this project is more complicated than it started out as. Originally it was supposed to be a quick one week thing, simple voltage regulators, no high speed ADC, and the LCD for ADC measurements from the PIC. Instead, now I am aiming to learn about CPLD's, the IDE for xilinx, and how to set up high level functions using low level logic gates.

Some updates:
- I will end up using the pic32 I selected earlier due to it being compatible with my pickit2, and I am already familiar with the entire PIC series of MCU's as well as the IDE and whatnot. For my next project, the rover, I will use an ARM mcu probably
- I am learning how to input things for xilinx chips using the schematic view in the IDE
- Learning how to make registers and things like that from logic in a CPLD
- Learning the xilinx IDE, which is a bit confusing at first I must say. Plan ahead which displays the inner chip connections is AWESOME!
====== Design Changes ======
- the CPLD will take care of all high speed logic (address increment for ADC, clocking for the ADC, depending on use can send flag to MCU)
- Will use a PIC32 as the controller for the LCD, connect to the buttons/dials, connect to a speaker, basically the slower main things
- the Propeller will take data from each ADC and the CPLD and will display it on a separate VGA LCD as well as other things I think of
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Re: Power supply using a 2U rack chassis (56K warning)

Postby hak8or » Tue Sep 06, 2011 1:15 am

Something quick to update everyone.
I am currently learning how to use schematic entry in the Xilinx IDE, and I am thinking out how to pack in everything I need into the CPLD.

Image
http://8486.a.hostable.me/PSU_BIG/CPLD_PROGRESS_1.PNG
The top you see eight squares, each is a 4 bit latch, which gives me four eight bit registers. I will have seven registers total in the end which consist of: ADC value, Address register one, address register two, address register three, address register four, Clock division register, and a misc register for Enable/disable adc, enable/disable memory, memory test (writes FF and verifies), full reset, things like that. Time is very not forgiving for me lately. :P

Here is the PDF of it so far: http://archive.hak8or.com/PSU_BIG/CPLD_PROGRESS_1.pdf
Last edited by hak8or on Mon Apr 06, 2015 10:05 pm, edited 1 time in total.
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Re: Power supply using a 2U rack chassis (56K warning)

Postby ian » Tue Sep 06, 2011 1:56 am

Nice looking Xilinx schematic. I bet it was an exercise in frustration to get that baby entered :)
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Re: Power supply using a 2U rack chassis (56K warning)

Postby hak8or » Tue Sep 06, 2011 9:51 am

ian wrote:Nice looking Xilinx schematic. I bet it was an exercise in frustration to get that baby entered :)


Oh god yes! :P It is a very frustrating experience for me. The IDE always thinks that you want the wires to be connected to the gate or macro, even when you rotate it. To get the wires to disconnect from the macro/gate, you have to cut the item and then paste it elsewhere. If you want to delete part of a wire, you can't, you have to delete the entire wire and redraw it from scratch. To move a wire, sometimes the IDE refuses to move the wire, sometimes when you drag the wire elsewhere, it drags the entire wire, sometimes only part of the wire.

There are a few more annoyances, but yes, it was a test in my patience to get that much in so far. :P

Edit: Let me correct a few things I said earlier. After working with the IDE some more, I saw an option to "select options" which lets me fix most of the things I said above.

Image
http://archive.hak8or.com/PSU_BIG/CPLD_IDE_1.png

One other annoyance I have noticed is the "auto route" for schematic views. I was trying to connect a wire to another wire in a bus, but the wire kept going around the bus and connecting to it from the other direction. I had to put the wire very close to the bus, and then it would properly connect to the bus. There is maybe an option in the IDE to turn off the "auto route" feature in the IDE and I did not find it, so I will refrain from saying that the IDE was at fault.
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Re: Power supply using a 2U rack chassis (56K warning)

Postby hak8or » Tue Sep 06, 2011 4:39 pm

This is the most I can do for today I guess, here is my progress for today:

Image
http://8486.a.hostable.me/PSU_BIG/CPLD_PROGRESS_2.PNG

PDF: http://archive.hak8or.com/PSU_BIG/CPLD_PROGRESS_2.pdf
Lots and lots more to do, and I forgot to put in the buffers to the "registers" for the address.
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Re: Power supply using a 2U rack chassis (56K warning)

Postby rsdio » Wed Sep 07, 2011 4:56 am

Do the Xilinx tools allow for the creation of a 'bus'? In Eagle, you can create a bus and then just draw your 4 or 8 wires from a chip to a 'bus' symbol which represents the group. This make your schematic much easier to read, but you'll have to be careful to connect everything on both ends - labels help. I have no idea if a similar option is available in the Xilinx tools, but maybe someone will be able to make use of the suggestion in their Eagle use.
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Re: Power supply using a 2U rack chassis (56K warning)

Postby bearmos » Wed Sep 07, 2011 6:51 am

rsdio wrote:Do the Xilinx tools allow for the creation of a 'bus'?

i was thinking the same thing - structural VHDL allows for it in the code - you'd think it would be natural for the Xilinx IDE to support it as well - i've never used the Xilinx IDE, personally, though - sounds painful!
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Re: Power supply using a 2U rack chassis (56K warning)

Postby hak8or » Wed Sep 07, 2011 9:55 am

The xilinx tools do allow for the creation of a bus, but I do not want to use it in this case because .. well ... wait, why am I not using a bus?

Oh, yes. I had to open the xilinx schematic entry window and look at my schematic again. It simply helps me see what I am doing. It does make sense to be using a bus when doing something like this, but I want to have each of the connections visible to me within reason to aid in understanding what I am doing.

I am using a bus for connecting the counters to the address bus, but that is it pretty much. Also, I want the bus line to be thicker than xilinx gives me, so instead I am just using individual lines in each bus. :P
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Re: Power supply using a 2U rack chassis (56K warning)

Postby hak8or » Wed Sep 07, 2011 1:42 pm

Another update so far today. I don't think I will get any more done today. I am happy to say though that I am learning all the quirks of the Xilinx IDE. I will email Xilinx some suggestions/feedback, specifically about the movement of things in the schematic view, hopefully they can nail it like Altium did so.

I have to decrease the number of stuff I am doing in the CPLD, I originally intended for it to fit in a 36 macrocell cpld, but turns out I needed more. Then I jumped to a $2 CPLD which had 72 macrocells, turns out I needed even more. The next jump from Xilinx in digikey is a $6 CPLD with 128 macrocells (Coolrunner 2). At that price I can just get a FPGA, specifically a spartan 3A, and not worry about JTAG, instead just worry about a SPI flash which would make things much easier for me.

Anyways, here is my progress! I added in the address and counter for the RAM, I now have to work on the clock divider and if I will be using an FPGA, I will add in the button functionality instead residing in the PIC. Rethinking quite a bit lately too. Also, yes I know that the address latches are all wired up together, I am going to fix that later. If there are any mistakes, someone point them out? :)

Image
http://archive.hak8or.com/PSU_BIG/CPLD_PROGRESS_3.PNG

The pdf: http://archive.hak8or.com/PSU_BIG/CPLD_PROGRESS_3.pdf
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Re: Power supply using a 2U rack chassis (56K warning)

Postby hak8or » Thu Sep 08, 2011 12:08 am

I got home and I wanted to quickly view the schematic again, so I opened the xilinx IDE.

It says:
ERROR: Could not find symbol "buft4"
ERROR: Could not find symbol "bufe4"

I close and open the IDE, still same error, I open the project using the 32 bit version of the xilinx IDE, and again the same thing. I check what buffers are avalible, and apparently only the single buffers are available.
So I think, maybe an update will help, it will check if anything is missing and download it. Turns out that to update the IDE to a newer revision, I have to download the entire FOUR GIG file. Really xilinx, you are a multi billion company which works with FPGA's, which to use you need to have a proper IDE, and you cannot get incremental updates?

I must say, I am extremely peeved at the symbols magically being not available suddenly, and that to update the suite I need to re download the entire four gig file.

Edit: Turns out that that sort of buffer is not available on FPGA's. As I made the design, I went to a larger chip with every progress in the design, but I did not close the IDE. When I opened the IDE again, it just then checked that the buffers are not available on the chip I selected.
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Re: Power supply using a 2U rack chassis (56K warning)

Postby ian » Thu Sep 08, 2011 2:02 am

I always have problems flipping and moving parts, and it often won't autoroute to somewhere due to some clearance you can't see at all. The frustration experienced with the cct entry is a well known bug ;) You would not be alone in hating it. I used it for a long time and eventually even learning VHDL/Verilog was less painful (not that I would encourage you to do that, it was a year with schematics before I was ready to try code).
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Re: Power supply using a 2U rack chassis (56K warning)

Postby bearmos » Thu Sep 08, 2011 6:45 am

back when i was using ISE Web Pack (not sure if that's still the name) the schematics were viewed by my professor as a cute feature, rather than something useful! A lot of times, we would use an external flow charting tool to quickly sketch what we were making, rather than get bogged down in the tedium of schematic entry.

If you have a solid digital logic background the VHDL is a bit cumbersome, but no more than any new language - mainly due to syntax.

Then, eventually, you'll get sick of writing the repetitive VHDL (if you're doing purely structural, building everything from NAND gates) - that's where the hacked together VHDL generators come in - and the fun really begins!

I need to get back into this, it's been too long!
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