XC9500XL CPLD breakout board Sink Source Current Question

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XC9500XL CPLD breakout board Sink Source Current Question

Postby turc86 » Mon Dec 05, 2016 4:19 pm

On the following page: http://dangerousprototypes.com/docs/XC9 ... kout_board under the Button and LEDs section, it states that the CPLD can only sink/source 8mA. However, on Figure 16 in the "I/V Curves for Xilinx FPGA and CPLD Familes" datasheet (sorry, it's not letting me add an outside link to this post) states that it can sink up to ~72mA at 3V. Am I reading the xilinx datasheet correctly?
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Re: XC9500XL CPLD breakout board Sink Source Current Questio

Postby tormodvolden » Mon Jan 02, 2017 11:48 am

What the IOL curve in Figure 16* says is that if the logic output level is low, but you sink e.g. 70 mA, the output voltage will rise to 2V (and if you try to sink more it seems to saturate at 72 mA and voltage levels can rise well beyond 3V).

So it depends on the threshold voltages of whatever is connected and should read the logic level. If you can tolerate that the "low" voltage rises to e.g. 1.0 V, you can sink 45 mA.

The IOH curve is for sourcing, when you have a "high" logic output level. E.g. if you can live with the "high" level dropping down to 2 V you can source almost 30 mA.

This is explained on page 12 in the UG445 document from Xilinx.

Sourcing and sinking add to the total power dissipation, which might limit you even if individual pins are within spec.

*) from http://www.xilinx.com/support/documenta ... app150.pdf
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