Open Bench Logic Sniffer with 64MB capture buffer

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Open Bench Logic Sniffer with 64MB capture buffer

Postby mkarlsson » Wed Oct 02, 2013 11:07 am

A new version of the Open Bench Logic Sniffer code is now available for Pipstrello-LX45. This version has the capture buffer increased to 64 MB by using the onboard LPDRAM instead of using internal BRAM. The capture rate is still the same, i.e. it still support 200 MHz 8 and 16-bit capture as well as 100 MHz 32-bit capture. The serial communication speed is set to 921600 baud.

The original SUMP protocol unfortunately has a capture size limitation (in hardware) to a maximum of 256k samples (512k samples in mux mode). This version of the verilog code has an alternative set of capture size registers that will allow up to 256M samples. However, the SUMP client on the PC must be modified to take advantage of the new registers so I have modifiled JaWi's OLS client to allow longer captures. BTW, it will also work with the current release of the SUMP client but with the capture size limitation mentioned above.

Here is a link to a zip file that has the bit file, the full Xilinx ISE project and the modified version of JaWi's OLS client:
http://www.saanlima.com/download/pipistrello-v2.0/Pipistrello_OLS_64M.zip

More information about Pipstrello can be found here:
http://pipistrello.saanlima.com/index.php?title=Welcome_to_Pipistrello
http://saanlima.com/store/index.php?route=product/product&product_id=51

Enjoy!
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Re: Open Bench Logic Sniffer with 64MB capture buffer

Postby Bingo » Wed Oct 02, 2013 2:04 pm

That's cool

Where does the board ship from ?

If it's outside EU , i'll be hit by serious vat & vat handling charges here in DK

/Bingo
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Re: Open Bench Logic Sniffer with 64MB capture buffer

Postby mkarlsson » Wed Oct 02, 2013 2:51 pm

The board ships from US so you probably can't avoid VAT (unless you are lucky and the package will get there without going through customs).
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Re: Open Bench Logic Sniffer with 64MB capture buffer

Postby Qwlciguk » Thu Oct 03, 2013 10:02 am

mkarlsson wrote:A new version of the Open Bench Logic Sniffer code is now available for Pipstrello-LX45. This version has the capture buffer increased to 64 MB by using the onboard LPDRAM instead of using internal BRAM. The capture rate is still the same, i.e. it still support 200 MHz 8 and 16-bit capture as well as 100 MHz 32-bit capture. The serial communication speed is set to 921600 baud.

The original SUMP protocol unfortunately has a capture size limitation (in hardware) to a maximum of 256k samples (512k samples in mux mode). This version of the verilog code has an alternative set of capture size registers that will allow up to 256M samples. However, the SUMP client on the PC must be modified to take advantage of the new registers so I have modifiled JaWi's OLS client to allow longer captures. BTW, it will also work with the current release of the SUMP client but with the capture size limitation mentioned above.

Here is a link to a zip file that has the bit file, the full Xilinx ISE project and the modified version of JaWi's OLS client:
http://www.saanlima.com/download/pipistrello-v2.0/Pipistrello_OLS_64M.zip

More information about Pipstrello can be found here:
http://pipistrello.saanlima.com/index.php?title=Welcome_to_Pipistrello
http://saanlima.com/store/index.php?route=product/product&product_id=51

Enjoy!


Wow, this is incredible. Only one concern here though. 64Meg of data at 921600 baud is gonna take a long time to transfer. On the order of 580 seconds to move the data actually and that is assuming no other overhead. Even if you had kept the SPI interface used on the OBLS, I'm not sure that it would reduce that transfer time sufficiently. The FTDI USB/SER chip on the Pipistrello can certainly do SPI, but there probably isn't any way to make the host think it is talking to a simple USB emulated serial port whilst doing SPI to the Spartan6. That is one strength of the OBLS design with it's PIC, but as I said, it's probably not enough to get the transfer time into a reasonable range anyway. I expect that you're stuck with the FTDI chip on the Pipistrello in any case. Since you already mod'd the client software for capture length, maybe the next thing would be to move away from serial port emulation entirely and go with the parallel FIFO mode of the FTDI?
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Re: Open Bench Logic Sniffer with 64MB capture buffer

Postby mkarlsson » Thu Oct 03, 2013 11:33 am

Yeah, FIFO mode is the way to go.

The first version of Pipistrello (v1) did have synchronous FIFO mode support for applications like this and I have ported the verilog code over to use that instead of serial communication. I wrote a quick test (just a small C program linked with ftd2xx) that would setup a 64 MB capture and then receive the data, and got over 29 MB/s transfer speed.

The version of Pipistrello that's now available (v2) rearranged the FTDI ports to get JTAG on the A port so only async FIFO mode on port B is now available. Still, this should do about 9 MB/s so a full 64 MB capture would take about 7 seconds to download. I will change the code for async FIFO interface and verify this number.

BTW, I have been in contact with Jan Williem (the author of the JaWi OLS client) and he is very interested in adding FIFO support to the client.
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