Demon 3.07 verilog code ported to Pipistrello LX45

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Demon 3.07 verilog code ported to Pipistrello LX45

Postby mkarlsson » Mon Sep 09, 2013 6:23 pm

FYI, I have ported the Demon 3.07 code to Pipistrello LX45 FPGA board with the following changes:

1) The sample buffer size is increased by a factor of 8 from 24kB to 192kB
2) The interface is changed to serial (Pipistrello uses a FTDI 2232H High-speed USB chip)
3) The baud rate is increased from 115200 to 921600 to reduce the data upload time
4) The meta data has changed to indicated Pipistello implementation

I believe this is the largest buffer size of any of the "SUMP" implementations. It runs great with the latest JaWi OLS Java client.

The implementation uses about 22% of the slices and 96 block rams (out of 116 total).
BTW, removing the advanced triggers reduce the size to about 7% of the slices making it quite possible to have this as an internal logic analyzer in a FPGA project.

More info and links to the complete XISE project and the bit file can be found at the saanlima forums (sight, the link got blocked, I guess you just have to google "pipistrello fpga").

Magnus
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Re: Demon 3.07 verilog code ported to Pipistrello LX45

Postby mkarlsson » Wed Sep 11, 2013 2:06 am

Screen shots:
Image
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Re: Demon 3.07 verilog code ported to Pipistrello LX45

Postby mkarlsson » Fri Sep 13, 2013 10:19 am

Here is a link to information about the project including the complete XISE project for download:
http://saanlima.com/forum/viewtopic.php?f=9&t=8
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