FPGA Verilog "Demon Core" + AdvTrigger + Meta + RLE + Timing

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Re: FPGA Verilog Port + AdvTriggers + Meta + RLE + Timing Fi

Postby ian » Sun Jan 30, 2011 10:57 am

I loaded the v2.4 firmware from another thread and the latest Verilog 4 bitstream. I ran the beta 4 Jawi client, and ran portmon to get a look at the activity. In this particular capture it looks like there is no reply to the 0x04 query. I'll do some manual probing now.
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Re: FPGA Verilog Port + AdvTriggers + Meta + RLE + Timing Fi

Postby dogsbody » Sun Jan 30, 2011 12:56 pm

Query was disabled in release4, because I wasent sure if it'd crash OLS or not. I subsequently found it was the MSB ordered long data that caused the problem (I think).

Anyway, I uploaded meta3 for Jawi to evaluate:

viewtopic.php?f=57&t=1198&start=30#p16745

However, that's when all the problems started. I'm running XP SP3. Can't understand why 0.9.2 works perfectly & 0.9.3 dies on capture, with an exception in the rxtxserial.dll library. I've tried updating the system Java to the latest release. I've flushed the Java caches & felix-caches. Tried installing under the root directory. Dunno what else to try. Ideas?
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Re: FPGA Verilog Port + AdvTriggers + Meta + RLE + Timing Fi

Postby dogsbody » Mon Jan 31, 2011 12:16 am

Update! OLS 0.9.3 works, along with RLE & Meta data, but is -sensitive- to high COM port numbers. If your Logic Sniffer appears on port COM10 or higher, it will fail.

On Windows, go into the device manager. Select Ports (COM & LPT). Open properties on port the Logic Sniffer currently resides (ie: COM11). Click on "Port Settings" tab. Click "Advanced..." button. On bottom of dialog is "COM Port Number". Choose one less than 10. Click OK, and OK again. Open 0.9.3, select the new COM port and it should work!

Windows might say the new COM is in "use", but likely just reserved it for another unplugged USB COM port device. In other words, it's safe to ignore the warning.

Hopefully Jawi can now fix the bug properly to avoid anguish among the newbies. :-)
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Re: FPGA Verilog Port + AdvTriggers + Meta + RLE + Timing Fi

Postby ian » Mon Jan 31, 2011 2:30 am

Great news, I'm glad you got it going! That frees up my morning for some other debugging :)
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Re: FPGA Verilog Port + AdvTriggers + Meta + RLE + Timing Fi

Postby jawi » Mon Jan 31, 2011 5:53 am

I've uploaded a new beta (6) which should solve the COM-port bug on Windows platforms. See this post on the client releases topic for details.

Now on with all other issues I came across recently... ;)
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Re: FPGA Verilog Port + AdvTriggers + Meta + RLE + Timing Fi

Postby ian » Mon Jan 31, 2011 6:37 am

I tried it on XP-SP3 with both meta3 and verilog4 bitstreams, it seems to work ok (no crashing).
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Re: FPGA Verilog Port + AdvTriggers + Meta + RLE + Timing Fi

Postby jack.gassett » Mon Jan 31, 2011 1:09 pm

It looks like things are starting to solidify, I would like to get the code officially checked into svn and make an official Test Release.

@dogsbody
Are you ok with svn? If you create an account at gadgetforge.gadgetfactory.net I will add you as a developer on the OLS project so you can check in code.
If you have concerns or prefer something else just let me know, I should be online in the #GadgetForge IRC channel on Freenode all day.

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Re: FPGA Verilog Port + AdvTriggers + Meta + RLE + Timing Fi

Postby dogsbody » Mon Jan 31, 2011 1:29 pm

jack.gassett wrote:Are you ok with svn?

If I need to use SVN, I'll use SVN. :-) I think I've got it installed in a VM somewhere. The flavor I have "helpfully" plugs itself into Windows Explorer, so I relegated it.

I'll upload the source when I get home tonight.
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Re: FPGA Verilog Port + AdvTriggers + Meta + RLE + Timing Fi

Postby jack.gassett » Mon Jan 31, 2011 1:36 pm

@dogsbody

I use TortoiseSVN under Windows, it is a nice interface. I can get the initial code checked into svn so you don't have to worry about all of that hassle.

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Re: FPGA Verilog Port + AdvTriggers + Meta + RLE + Timing Fi

Postby dogsbody » Mon Jan 31, 2011 1:50 pm

Sure, that's fine. There are some minor tweaks I've made since release 4, but sounds like a good starting point.

In my earlier quest to get RLE & OLS working (before I discovered the speed grade thing), I disabled meta & added some synthesis directives to the BRAM instances that can foul up the first output sample.

I've also registered as "dogsbody" on your site now. Cheers!
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Re: FPGA Verilog Port + AdvTriggers + Meta + RLE + Timing Fi

Postby dogsbody » Wed Feb 02, 2011 4:50 am

I've just posted Release 5 (see first post in thread).

This image restores meta data, and has minor fixes to ensure the ram captures what the advanced trigger wants captured (not the cycle before or after). Also ensures rle-encoder and sram interfaces reset properly to known state, and undoes some unnecessary changes made during early rle debug.

I've documented some "extra" RLE-modes that have been lurking for a while. If used by the client, they can nearly double the storage of non-changing data. Not bad for a couple extra lines of verilog.

Lastly, the verilog port is now on the Gadget Factory Official SVN! Thanks to Jack for hand holding me through the process!

Note: Please be sure to use Jawi's 0.9.3-b6 release (or newer)! Solid RLE support & all Windows issues vanquished!

Enjoy!
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Re: FPGA Verilog Port + AdvTriggers + Meta + RLE + Timing Fi

Postby ian » Wed Feb 02, 2011 7:16 am

Here's the bitstreams in a .zip for anyone following without SVN mojo.
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Re: FPGA Verilog Port + AdvTriggers + Meta + RLE + Timing Fi

Postby dogsbody » Wed Feb 02, 2011 12:25 pm

Good idea! Although my release zips have the bitstreams, many people would probably prefer not wading through the source files. I've attached your Verilog-5 zip to the first post. Also tossed in a couple comments for newbies. Cheers!
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Re: FPGA Verilog Port + AdvTriggers + Meta + RLE + Timing Fi

Postby ian » Wed Feb 02, 2011 12:47 pm

I forgot to try the first post :) I followed the link to SVN and the download link dumped everything in my browser as text. It seems like several people are following and testing, so I thought that might help someone else out and score a few extra testers. I'll stay quiet and just check the first post from now on :)
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Re: FPGA Verilog Port + AdvTriggers + Meta + RLE + Timing Fi

Postby ian » Mon Feb 07, 2011 12:22 pm

This firmware (v2.6) has a faster PIC->FPGA SPI clock to take advantage of the increased abilities of the new core. This will be buggy with the old core, though I have not seen issues with the new core:

viewtopic.php?f=23&t=1802
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