Upverter editorial, original copy

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Re: Upverter editorial, original copy

Postby arhi » Mon Sep 26, 2011 3:49 pm

brian wrote:I am sorry if what I said isn't clear enough.

nothing to be sorry about, I was not trying to say that what you said is wrong, just that I don't get how a one way propagation of data is related to DRC. For e.g. in Proteus if I want to change what gate I'm using on 74hc14 I have a single click and I will change the gate used. The change will be on pcb and on schematic after that single click. Same with Altium. With KiCAD I have to go back to schematic, reconnect the gate, save netlist, open in cvpcb, check, save netlist, reload netlist back in pcbnew (and hope nothing bad would happen - ok this is irrelevant to this story) and I'm done. You are right, not 15 steps, only 5 and each of them is more then one click - compared to a single click in Proteus/Altium. Ok, that might be a lot of "work" to be implemented in KiCAD.

I *do* agree 100% that this 5 additional steps are worth the few hundred $$ Proteus cost (295GBP for 1000 nodes in netlists limit, 395$ for 2000 nodes in netlists limit, 1225GBP for unlimited everything option so yes, expensive, not unobtainable but very expensive, especially compared to FOSS tool like KiCAD!!). What I *do not* agree is that "this is the proper way to do things".

Nor I understand how this "one way street" helps with DRC. I'm not being "smart ass" here, it is a question I'd like to figure out answer to as there's obviously something I'm looking at wrong here, and I don't agree it's because "it is not working the way I expect it to". Most apps don't think how I expect them to - thing is that I want them to be able to do what I need them to, and then you open the manual and read *how* to do it. Problem I see with KiCAD is that stuff is not doable (where every pro tool make it happen) and then ppl tell me "that's how it supposed to be done" ?!


brian wrote:the people who wrote it aren't crazy.


I had a pleasure of meeting many open source legends because of the work I do and all my colleagues are open source developers, and I can say that I do not know a single open source developer that isn't crazy. I see that as a positive thing as "regular" ppl are boring and never able to achieve anything worth mentioning, and most of them would be insulted on what you just say :D :D :D

I know you don't like it but I get the impression it is mostly because it doesn't work like you expect. If you can afford Altium great, it is a better tool, but most of us cannot.

I can afford it, but I don't want to. I got me a small licence of Proteus as I like it and it's cheaper, Altium is 1000-6000$ compared to 250$ Proteus is starting at (limited to 500 nodes in netlist). I spent already more then 200 hours with kicad trying to use it and I got used to it. Schematic capture is not as nice but works and I can now make a schematic "almost" as fast as with Proteus. Problem starts when you want to go further from schematic...


brian wrote:But there are applications where you might want to mismatch the pin and footprint count.

That is "exception", meaning you need that in under 30% cases. So why not allow filtering by pin count and then add a "hit me with everything" button instead of filtering by name ?! Killing the usability to allow "exceptions" to be covered by basic behavior is never a good idea. Exceptions are called exceptions for reason. But that's another story

brian wrote:The best solution remains explicit filtering.


Why not have filtering on all properties of the footprint, if you can filter by name, why not by pin count too?

Choosing footprints is a nasty part of every cad program. Many have some serious limitations (kicad is not close to what some limit you with). It is a lot of work and we all know how foss apps are made ... I see a huge potential in KiCAD but I also see a lot of, what I see as, misdirection's and fanaticism. As I said - I don't mind the "it's not implemented now, and is not planned for near future as we have more important things to deal with" answer. And I agree 100% that, for e.g. back annotation or filtering footprints by no of pins is far from being priority. What I do not agree with is "filtering by pin count is not how you should assign your footprint because sometimes you want to use part that has different pin count" and stuff like "back annotation is wrong".

You said that this way DRC is preserved. That is something that sounds like an argument that might explain why back annotation is wrong. Cool, but I don't see it. I would like argument explained so I can rethink my position and maybe agree with the assessment I'm presented with.
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Re: Upverter editorial, original copy

Postby brian » Mon Sep 26, 2011 4:47 pm

arhi wrote:I don't get how a one way propagation of data is related to DRC.


I haven't used back annotation extensively in other packages. However if I could connect a net to a pin not in the netlist while routing I could make a DRC error. While DRC would still catch the error when run and flag it, KiCAD generally prevents you from connecting wrong nets as you route (and other DRC). To allow netlist modification on the PCB you would need to remove this DRC enforcement or create a separate mode.

arhi wrote:With KiCAD I have to go back to schematic, reconnect the gate, save netlist, open in cvpcb, check, save netlist, reload netlist back in pcbnew (and hope nothing bad would happen - ok this is irrelevant to this story) and I'm done.


So you know... CVpcb is not needed. CVpcb is only used to associate symbols with footprints. You go to schematic make the change + 2 clicks to export the netlist, 2 clicks to import it. You generally only need CVpcb once. If you add 4 clicks every change that might be quite tedious, but I suspect you will see the 5 pins that need to be changed and the overhead will only be 4 clicks on top of the 10 or so routing clicks you would have had.

I think the suggestion to allow for more kind of filtering is something you should certainly put on the wishlist on KiCAD's launchpad page. Proper use of name filtering on defining symbols makes KiCAD the same depth of choosing as Eagle except no default.
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Re: Upverter editorial, original copy

Postby arhi » Mon Sep 26, 2011 5:38 pm

brian wrote:I haven't used back annotation extensively in other packages. However if I could connect a net to a pin not in the netlist while routing I could make a DRC error. While DRC would still catch the error when run and flag it, KiCAD generally prevents you from connecting wrong nets as you route (and other DRC). To allow netlist modification on the PCB you would need to remove this DRC enforcement or create a separate mode.


Not sure I follow 100% .. (I haven't spent too much time in the pcb capture part of kicad, only schematic) but if you rotate a part in pcb layout you will make DRC error... if you route A and B gates of the 74hc14 and then you see that it would be better to swap gate A and gate C and go to schematic and reconnect the gates going back to pcb will show DRC error (not sure if KiCAD would show the error immediately, Proteus for e.g. show drc errors real time, no need to execute separate process to find them - anyhow the drc error will be there). The bac annotation actually helps here as you physically take the link to the gate A and move it to gate C in the PCB capture part so you actually immediately see what's going on ... it's faster, cleaner and actually safer as you directly see what's and where going on. Doing this trough schematic is not only slower but way harder to see as on pcb layout you actually see where each gate is on board and on schematic layout you have no clue where they are on chip as you see each gate separately. So I still don't see how changing anything in schematic and reloading the net in pcb layout helps preventing DRC errors on pcb layout as you are actually making changes in the part of the app where you don't have a clear view of a pcb and parts ...




brian wrote:So you know... CVpcb is not needed. CVpcb is only used to associate symbols with footprints. You go to schematic make the change + 2 clicks to export the netlist, 2 clicks to import it. You generally only need CVpcb once. If you add 4 clicks every change that might be quite tedious, but I suspect you will see the 5 pins that need to be changed and the overhead will only be 4 clicks on top of the 10 or so routing clicks you would have had.


My bad here, I believed I always had to go trough cvpcb so the procedure could be skipped by a step out of three (third of the process less, not bad), good to know; especially as cvpcb is the worse part of the whole system, it sooooooo darn ugly and hard to navigate and missing basic stuff ... but that is only a single app, and imho easiest one to rewrite from scratch if required (no fancy drawing gui stuff, few forms and some parsing .. should be an easy one to rewrite).

brian wrote:Proper use of name filtering on defining symbols makes KiCAD the same depth of choosing as Eagle except no default.

Lot of ppl compare KiCAD to Eagle. I'm not a big fan of Eagle; except for way richer libraries and way better flow from schematic to pcb and back, Eagle suffers from many issues KiCAD has, and KiCAD, even with whole bunch of bugs (redraw being required too many times being one of them) has faster schematic capture then Eagle!!

WRT "proper use of name filters", sorry, I have to strongly disagree. I want to call package SIL5, DIP20, SDIP18, 0805, 1206... not "TH_SIL_5" or "TH_DIP_20" or "SM_0805_2" ... and I want to have parameter that will hold number of pins in each of them or ability to read number of pins from the library itself (should be easy as each pin needs to be named/numbered anyhow) and ability to filter on that value ... making the fooprint name contain all details about the footprint is seriously a huge mistake, trust me I seen that "temporary workaround" mess few serious projects .. There's a name, there's description, there's parameters (no of pins, pitch, length, width, height, type:trough-hole,smd ...) ...

Anyhow so far the major issue I have is with "that's how it supposed to be" I hear so often .. as that shows the lack of knowledge and direction .. I'm actually fairly pleased with the solution so far ..

On the other hand I'm looking at the gEDA a bit more past few weeks as it seems to have more ppl working on it and it seems to be more robust in the way it's built ... it's gtk so works fine with gnome (I don't like kde), no "refresh bugs" :) and schematic is also seriously fast. I have not tried to make my own package / library yet and I have not tried to make a pcb at all with it but first time I find a free day I will try it out .. as it seems like something I could even contribute to (source looks waaaaaaaay neater then kicad)
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Re: Upverter editorial, original copy

Postby brian » Mon Sep 26, 2011 6:12 pm

My top need in KiCAD is not back annotation but PCB trace length matching. That is easy in Altium not not really available at all in KiCAD. Each person has their own needs.

To try to explain the DRC thing one more time, all I mean is that if you attempt to attached NET1 to NET2 the router won't let you, because it would violate DRC.

For example: say you again have 2 pins A and B, and you can swap their function in the CPLD. The schematic has A connected to C (NET1) and B connected to D (NET2). You want A->D and B->C now cause you see that is better for layout. Because KiCAD prevents you from connecting NET1 wrongly to NET2 you can't make this change in PCBnew. The DRC is enforced as you route. If you change the NET list via EEschemia you can make the change until you do you can't route that way.

My understanding of what you want to do as far as back annotation is you want to make this change (ignore the NETlist and and have the schematic reflect the change). Perhaps is is analogous to a strongly typed language verse a weakly typed one. It can be a lot faster to write something in a scripting language but there is more room for making a mistake?

As you point out rewriting CVpcb is really easy, one could do it in a few days at most and implement all kinds of filtering if you desire them.
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Re: Upverter editorial, original copy

Postby arhi » Mon Sep 26, 2011 7:04 pm

brian wrote:My top need in KiCAD is not back annotation but PCB trace length matching.


I need that too from time to time, unfortunately small Proteus licence don't have it (not sure even if the most pimped up Proteus have it) and Altium is, as you mentioned, expensive as hell :(

brian wrote:For example: say you again have 2 pins A and B, and you can swap their function in the CPLD. The schematic has A connected to C (NET1) and B connected to D (NET2). You want A->D and B->C now cause you see that is better for layout. Because KiCAD prevents you from connecting NET1 wrongly to NET2 you can't make this change in PCBnew. The DRC is enforced as you route. If you change the NET list via EEschemia you can make the change until you do you can't route that way.


Clear now. You can't do this in Proteus either by using "regular" connection. There is a special "key" that allow you to reconnect stuff in the pcb view. So you actually do exactly what you would do in schematic - you change the network node configuration - you modify the ratsnest connections .. if you do not modify the ratsnest / network configuration the pcb tool will not allow you to link the A->D and will yell DRC ERROR, but you can modify ratsnest directly and it will be reflected back in the schematic. It is really just a "faster way" to change stuff, this changes are bidirectional. I agree it would be stupid if pcb tool allows you to link A->D with a pcb trace and then "push that change back to schematic" .. Note also that you can only do this with pins on a package that are defined in the package as "interchangeable" or with a part "modules" (gates for e.g.), not with "any pin".

This is piece from Proteus ARES manual that might explain stuff bit cleaner then I did :)

PIN_SWAP/GATE SWAP
When used in conjunction with ISIS, ARES supports pin-swap/gate-swap changes to the connectivity whilst the layout is being routed. This means that you can choose to interchange the wiring to like pins, and/or interchange the use of like elements of multi-
element parts. A full discussion of how to prepare your library parts to exploit this feature is given in the ISIS manual, but from the ARES side there are two ways of using this feature:

Manual Pin-Swap/Gate-Swap
To perform a manual pin or gate swap
1. Select the Ratsnest icon.
2. Click right on the source pin. For a gate-swap, this can be any member of the gate. The ratsnest lines connected to the pin will highlight. In addition, legal destination pins will also highlight.
3. Hold down the left mouse button and drag the ratsnest lines to the required destination pin.
4. Release the left button. ARES will make the change, updating the ratsnest and force vectors as appropriate. In the case of a gate-swap, ARES will move other ratsnest lines automatically.

It is possible to combine a pin-swap and a gate-swap in one operation - for example, swapping input A gate 1 (pin 1) with input B gate 2 (pin 5) on a 7400 will do just this.

WARNING
Pin-swaps and Gate-swaps constitute changes to the connectivity of your design. ARES uses the pin-swap and gate-swap data specified in the ISIS libraries to decide what is, and is not, a valid swap. If there are errors in this data, then ARES may well suggest illegal swaps. We will not, under any circumstances, be held liable for any costs incurred or losses arising as result of such mishaps, whether the error be in your library parts or ours or in the software itself. We strongly recommend that you check that the swaps you make are really legal, and that your prototype your PCB prior to the manufacture of large quantities.


Automatic Gate-Swap Optimization
In the case of a board with a large number of possible gate-swaps (the SHIFTPCB sample is a spectacular example) in can be very hard to find the best arrangement. For these cases we have provided an automatic gate-swap optimizer.

To perform automatic gate swap optimization
1. Invoke the Gate-swap Optimizer command from the Tools menu.
2. ARES will make repeated passes trying the current set of possible swaps. The process repeats until no reduction in ratsnest length is achieved.

WARNING
The Gate-Swap Optimizer relies entirely on the gate-swap data specified in the ISIS component libraries to decide what is, and is not, a valid swap. If there are errors in this data, then the swap-optimizer is likely to make erroneous changes to the connectivity of
your design. We will not, under any circumstances, be held liable for any costs incurred or losses arising as result of such mishaps, whether the error be in your library parts or ours or in the software itself. We strongly recommend that this command be used only if you are going to prototype your PCB prior to manufacture.



Synchronization with the Schematic
Whether manual or automatic swaps are to be performed, it is a requirement that the changes can be reflected or ‘back-annotated’ into the schematic. For this to occur successfully, the schematic must not have been changed as well.
PROTEUS manages this by using the netlist file as a kind of token. If ARES cannot find an up to date netlist, it will not allow changes, and if ISIS makes changes it deletes the netlist. When ARES does make changes it writes out a back annotation file (extension ‘BAF’) the next time the PCB is saved. ISIS picks this up the next time it comes to the foreground. If ARES has changes that are not saved, ISIS will not allow changes. This scheme will prevent the making of simultaneous changes to both schematic and PCB in normal use. It is, of course, possible to circumvent the token mechanism by renaming files, editing and copying back, editing on other machines etc. If you deliberately contrive to modify the schematic and PCB at the same time, then you must live with the consequences! The only cure for such situations is to check carefully that the schematic and PCB are the same and then re-load the netlist into ARES.

Further discussion of pin-swap/gate-swap ...
Attachments
screenshot17.png
result of the gate swap optimizer
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Re: Upverter editorial, original copy

Postby arhi » Mon Sep 26, 2011 7:13 pm

This is just a single example ... not to mention some way simpler stuff like, I want to change "this resistor to be 0402" because I wanna fit it under this connector ... I do not want to start cvpcb to do it, why not just left click on resistor, set new footprint and save ..
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Re: Upverter editorial, original copy

Postby brian » Mon Sep 26, 2011 7:21 pm

You could do the same thing in a special mode added to PCBnew... However, the way EEschema works it would take a lot of effort to add it because you have to somehow draw a connection to reflect the changes. It just has dumb lines and then hidden dots on the grid for NETs. That is even if you just add a label to the nets in question it would have a hard time not making that label look bad (as written I think, though I haven't looked at the base code I have looked at all the text files it generates).

There are some hacks to do trace length matching using the microwave toolbox but it is pretty much a hack at the moment.
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Re: Upverter editorial, original copy

Postby arhi » Mon Sep 26, 2011 7:28 pm

However, the way EEschema works it would take a lot of effort to add it because you have to somehow draw a connection to reflect the changes


One of the reasons I'm looking at gEDA attm as it seems to be well written ... need to confirm that as I just gave source a fast check and it looked way nicer then kicad .. but gEDA's pcb editor looks even worse then kicad's so .. need to check if there's a point to all that
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Re: Upverter editorial, original copy

Postby brian » Tue Sep 27, 2011 1:30 am

arhi wrote:This is just a single example ... not to mention some way simpler stuff like, I want to change "this resistor to be 0402" because I wanna fit it under this connector ... I do not want to start cvpcb to do it, why not just left click on resistor, set new footprint and save ..


Again you don't have to use CVpcb to accomplish this task...

Hover over the module in PCBnew hit E (or right click and select edit). Click on change modules, and pick SM0402. It lets you change just that one or all the say 0603 to 0402 etc.

That change currently isn't put back in the netlist unless you do use CVpcb, so blinding reading the full netlist can cause a reversion if you start the board from scratch for instance. When reading a netlist you have the option of going with what the netlist (CVpcb) says or keeping your modules as they are, so it isn't a big deal. As long as you revision your board files, you can change the modules as much as you want without CVpcb. CVpcb is only used once to quickly assign all the symbols to modules after you finish designing the circuit. It is good practice to keep the net and board synced but even if you distribute the files to another user it won't get messed up, what footprint to use is in the board file.
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Re: Upverter editorial, original copy

Postby arhi » Tue Sep 27, 2011 3:42 am

It is even worse that you don't have to use cvpcb as

0. cvpcb set all resistors to 1206
1. I change R20 to 0402 in pcbnew
2. 10 days after that I add another capacitor to the board to add some filtering (so I have to do it in schematic -> cvpcb ->pcbnew)
3. The R20 is now reverted back to 1206, it messes up with connecor, breaks routing etc etc

I see that as a serious problem .. I don't see how hard is for the pcbnew to update that footprint back into the system ..
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Re: Upverter editorial, original copy

Postby brian » Tue Sep 27, 2011 12:05 pm

arhi wrote:It is even worse that you don't have to use cvpcb as

0. cvpcb set all resistors to 1206
1. I change R20 to 0402 in pcbnew
2. 10 days after that I add another capacitor to the board to add some filtering (so I have to do it in schematic -> cvpcb ->pcbnew)
3. The R20 is now reverted back to 1206, it messes up with connecor, breaks routing etc etc

I see that as a serious problem .. I don't see how hard is for the pcbnew to update that footprint back into the system ..


I'm sorry you are not correct. This breaking does not occur because the default is not to swap modules. As I said above "When reading a netlist you have the option of going with what the netlist (CVpcb) says or keeping your modules as they are, so it isn't a big deal."

You need to use KiCAD more and learn the basics, this is KiCAD 101. The default is to load only modules that do not exist in the board from the NET list so the situation you mention does not happen. You can reload from scratch as an override on NET import. It might be nice to have it update the NETlist from PCBnew but at this time it doesn't because that isn't the design flow they have chosen.

You should probably design at least a few boards in KiCAD then you would learn these things. Perhaps then you will be in a better position to offer suggestions to the developers and community on how to improve it.
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Re: Upverter editorial, original copy

Postby arhi » Wed Sep 28, 2011 2:20 am

I know you can chose to not load all modules but that's even worse imo as then you have wrong info in the netlist file. If they already made the 2 app's (schema and pcb) completely separate and they designed communication to go trough netlist file then netlist file has to have all the info... storing "some" footprint data in separate file is a serious flaw imo.

Anyhow the whole "we keep you from fscking up the drc by making it one way" only show ignorance towards how others do it as kicad actually just lack functionality and what they are "preventing" does not exist in any normal eda cad anyhow. I was just trying to figure out if there's any merit to what I was reading about it and there isn't... as for me being in position to suggest stuff, I don't suggest stuff if I'm unable to contribute and I don't see me contributing any time soon so I can push out some wish list but for suggestions some serious time need to pass first...
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Re: Upverter editorial, original copy

Postby brian » Wed Sep 28, 2011 11:21 am

Okay, you are welcome to your opinions. Just be aware you haven't discovered fully how KiCAD works IE thinking you need to use CVpcb each time, etc. I think it will be more efficient for you to learn by doing rather than point by point discussion with me. If you don't want to use KiCAD that's fine, but when you state things definitively that you have to do x-y-z and you don't you are going to mislead others, that is my only point. If you don't feel is is a comfortable workflow for you the good news is there are choices.
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Re: Upverter editorial, original copy

Postby arhi » Wed Sep 28, 2011 11:33 am

:D not having to use cvpcb in every step I was under impression is required is a step less but that's the only one. Everything else still stands - both workflow and inconsistencies .. Anyhow not really relevant to this discussion as I was only trying to figure out the "drc thingy" I heard too many times and I know what is meant by that now (and it does not prevent any errors any other cad would allow, just prevents same things all other cad tools prevent by limiting functionality instead of making a better interface). Everything else is question of "feel/likeness/familiarity/taste/..." and is not really relevant to the discussion here :)
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Re: Upverter editorial, original copy

Postby spanner888 » Wed Sep 28, 2011 11:21 pm

... just hijacking this thread in a slightly different direction.... The guys at http://www.ohwr.org/projects/ohr-meta/wiki/Foss-pcb have chosen to improve Kicad as a (the?) tool for use at CERN.
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