Core-memory emulation design question

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Core-memory emulation design question

Postby Bertho » Sat Aug 10, 2013 2:30 pm

Hi All,

I've been hacking a lot on flipdots, which some of you probably have seen. While at Ohm2013, I was talking about the internal function of the flipdots when the remark was made "that is just like core-memory". Well, yes, it is, so I tested it. You can see my write-up of using flipdots as core-memory at http://www.vagrearg.org/content/flipcoredotmemory.

The question, however, is one of design. I want to make a real version of flipdots-as-core-memory; one where you can read/write and see the actual content. That should be no problem were it not for the choice of components. I can use a) old-style 74xx logic, just in line with the old style of both flipdots and core-memory. Or, b) I can use a quick-and-dirty way by smacking a small micro-controller on there and do it all in software.

Option a) has charm, but is both more expensive, rather inflexible in operation and interfacing and harder to design.
Option b) is cheap(er), uses less space and is flexible for multiple types of interfacing, but there is some tension in the use of old vs. new components.

What should I do? Go for the easy/flexible way or for the retro way? Your input and comment is appreciated.
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Re: Core-memory emulation design question

Postby Sjaak » Sat Aug 10, 2013 3:03 pm

Use a cpld to emulate 74xx ? That would give you flexibility and 74xx logic :)
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Re: Core-memory emulation design question

Postby Bertho » Sat Aug 10, 2013 3:08 pm

Sjaak wrote:Use a cpld to emulate 74xx ? That would give you flexibility and 74xx logic :)

Sure, but then I still need support components for timing and. A micro-controller has it all, including A/D for adaptive timing.

There is not far from cpld to micro-controller. The distance 74xx to cpld is about as large as 74xx to micro-controller...
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Re: Core-memory emulation design question

Postby Sleepwalker3 » Sun Aug 11, 2013 1:50 pm

Well if concern over being retro, if it's a one-off, then you could use Bipolar PROMs (eg. 82S147, etc.), which is still retro, though not cheap to get these days, are OTP and you need a programmer that will handle them and the pro ones cost a heap (I have access to one if you went that way). Or you could use something that is semi-retro like PAL, though same problems as above, or GAL which is much more flexible, but still probably considered 'Retro' by many these days (again I can program them). Of course you could always use a retro processor along with EPROM. I have 8088, 8085, Z80, etc. stuff. I still have a core memory board floating around from an old CAI mini system.

Anyway, great article you did
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Re: Core-memory emulation design question

Postby Bertho » Sun Aug 11, 2013 3:25 pm

Sleepwalker3 wrote:Well if concern over being retro, if it's a one-off, then you could use Bipolar PROMs ...{snip}... retro processor along with EPROM. I have 8088, 8085, Z80, etc. stuff.

Actually, the real problem is not a processor as such. The problem I need to solve is one of the memory controller. Core-memory needs to have a read-write cycle with proper timing in order to get a hold of the data. The flipdots make it not easier because there are several constraints (current/voltage/timing wise) that need to be taken into account.

The sequence of operations is something like:
- precharge read
- read pulse
- read data latch
- precharge write
- write pulse (1 or 0 depending operation and data input)
- idle
Timing-wise it can be done at 20..25kHz clock and 12..13 clock-cycles.

A PAL/GAL(or cpld in general) would do the trick, taken it is a large enough one; there are quite a few states it needs to go through. I actually have a few old GALs somewhere in a box. However, it is definitely not a friendly design for others to replicate.

I like the idea of an (E)PROM. Then I can use it as a state-machine. There is some support hardware required, such as latches. My immediate estimate is that discrete logic would be about as large (physically) as an EPROM solution. I would need to check whether 8-bit would be enough for the entire state-machine. I guess that I would need two or three EPROMs to have enough room for all outputs, depending how much support logic I'd use.

Using retro CPUs as memory-controller would also make a lot of support hardware a requirement (the 8080 needs three supply voltages, last time I looked). It is much easier to embed all logic in one "modern" micro and be done with it. It would require almost no support hardware (except for the H-bridges and pulse-shaper).

Sleepwalker3 wrote: I still have a core memory board floating around from an old CAI mini system.

Does it still function? How is the memory controller made; discrete, CPLD or ASIC?

Sleepwalker3 wrote:Anyway, great article you did

Thanks.
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Re: Core-memory emulation design question

Postby blarson » Sun Aug 11, 2013 4:35 pm

By the time TTL was common, core memory had been mostly phased out. (With exceptions such as the space shuttle.) Most core controlers were RTL, DTL, or discrete.
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Re: Core-memory emulation design question

Postby Bertho » Sun Aug 11, 2013 5:12 pm

blarson wrote:By the time TTL was common, core memory had been mostly phased out. (With exceptions such as the space shuttle.) Most core controlers were RTL, DTL, or discrete.

True, the core-memories were phased out in late '60-ies early '70-ies and replaced with RAM chips (much in ECL design).

That said, integrated DTL logic is almost impossible to get nowadays. Completely discrete is rather complicated, considering the complexity of a memory controller.

So, if I understand correctly, your argument would then be "why bother with 74xx"? Good argument...
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Re: Core-memory emulation design question

Postby Sleepwalker3 » Mon Aug 12, 2013 12:06 am

Actually the core memory board is off a CAI 4-10 Naked-Mini (also dealt with the double width and more powerful 4-90 series and the 4-30 I think it was, so it may have been from that), which is (mostly) TTL based and was made from 1975/1976 from my recollection, so whilst it may have been on the way out, it was still being used (other than the space shuttle!). The main processor board on the 4-10 system had dynamic RAM with refresh cycles and all the rest (think I still have data sheets on that somewhere), but core memory was used around those years too. There was various technologies doing the rounds, Bubble memory was about for a short while, though that was a bit later I think

I can't recall the details of the 8080 voltage requirements, but the 8088 only needs 5V, as does Z80 and I think 8085 is the same. 2708 EPROMs needed 3 supplies, 2716 upwards were 5V and needed the HV for programming. 27C256, upwards are still available. I had some design info around somewhere for a state-machine using these, but was quite a long time ago, might have trouble digging it up. I have dozens of used 27256, but they are much slower than the CMOS versions to program (like 5 minutes versus about 30 seconds).

GALs are still around, in fact last time I checked the GAL22V10 was still being manufactured, but supplies of the GAL20V8, etc. are still fairly easy to obtain.

I didn't realise you were looking for something that others could produce easily, that makes it a lot harder of course, as most of this stuff needs a programmer. So yeah, from that, a modern microcontroller may well be the way to go, though the purists may disagree.
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Re: Core-memory emulation design question

Postby Bertho » Mon Aug 12, 2013 7:08 am

Sleepwalker3 wrote:I didn't realise you were looking for something that others could produce easily, that makes it a lot harder of course, as most of this stuff needs a programmer. So yeah, from that, a modern microcontroller may well be the way to go, though the purists may disagree.

That was why I asked ;-)

I did some designing with a single micro-controller:
flipcoredotmemory_2.png
Micro-controller based interface
(or as pdf:
flipcoredotmemory_2.pdf
Micro-controller based interface
(37.21 KiB) Downloaded 360 times
)
It has a very limited number of components. There are the H-bridges and some analog stuff that needs to be there filling a bit. The connectors are physically large. The real kicker is that a 32bit ARM is cheaper than an 8bit PIC/AVR for the number of gpios and functions I need.

My guess is that this would fit on a 50x100 PCB and the flipdot strip mounted perpendicular on a separate board. This makes it possible to have multiple (8) flipdot strips next to each other without spacing making a 7-byte register. A 40p ribbon-cable can be attached all the way (multidrop) and finally I get to reuse those old ATA harddrive cables ;-)
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Re: Core-memory emulation design question

Postby jaromir » Sat Aug 17, 2013 1:04 pm

Bertho wrote:The real kicker is that a 32bit ARM is cheaper than an 8bit PIC/AVR for the number of gpios and functions I need.

Just curious, what was the GPIO count and features list you needed?
I'm not going to persuade you to use another MCU, only doing my own personal research, this is another case study ;-)
my personal webpage - http://jaromir.xf.cz/ Update 05.06, project PIC500
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Re: Core-memory emulation design question

Postby Bertho » Sat Aug 17, 2013 1:23 pm

jaromir wrote:
Bertho wrote:The real kicker is that a 32bit ARM is cheaper than an 8bit PIC/AVR for the number of gpios and functions I need.
Just curious, what was the GPIO count and features list you needed?
I'm not going to persuade you to use another MCU, only doing my own personal research, this is another case study ;-)

GPIO:
- H-bridge control 7 or 16; with 7 I'd need 2x HC238 demultiplexers. Using 16 GPIO no extra hardware needed.
- address selection 3 or 7; with 3 you have binary selection, but that makes it difficult to do chaining (only 7 values used) due to non-continuous addressing. 7 address lines is easier.
- R/W, ACCESS, BUSY; 3 lines input control
- DIN/DOUT; 2 data lines
A/D:
- input voltage measurement for timing control
Comparator:
- trip level for memory content detection
Timers:
- pulse-control (charge/discharge timing)
- trip level delay timer

That makes 35 GPIO, 1 A/D and 1 comparator.

All that (and more) is available in an lpc1224/48LQFP for $2.50 (or less in volume).
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Re: Core-memory emulation design question

Postby Sleepwalker3 » Sat Aug 17, 2013 6:04 pm

Yeah I'd go the Arm and be done with it I think, why not mix new and old, there's nothing that says you can't! You aren't doing it to invent some new amazing piece of new tech, nor are you trying to recreate an exact period piece (as far as I know), so mix away! People mix Nixie tubes that were used in the 60's (actually most these days are just repro's I think) with modern micro's, so why not? It will be kind of a novelty seeing a ARM in hyperdrive, driving a memory technology like this that snails could go faster than :)
The only thing is, that if you are aiming this for other people to build, will they be able to program it? Having something that can be sorted with one of the common tools, a BP or just direct from USB from scratch would be a big advantage.

Now how about a Corei7 hooked up to my 8" floppy? Or one of the Paper-Tape readers to load the hex on that ARM9? ;)
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Re: Core-memory emulation design question

Postby Bertho » Sat Aug 17, 2013 6:27 pm

Sleepwalker3 wrote:Yeah I'd go the Arm and be done with it I think, why not mix new and old, there's nothing that says you can't!

My thought also, plus, it is a lot easier.

Sleepwalker3 wrote:The only thing is, that if you are aiming this for other people to build, will they be able to program it? Having something that can be sorted with one of the common tools, a BP or just direct from USB from scratch would be a big advantage.

I plan to use the lpc1224, which has ISP via serial. There is a simple program to download to the flash for any OS. My proposed design (see previous post) has both serial and SWD debug exported on headers, so you can simply attach there.

Sleepwalker3 wrote:Now how about a Corei7 hooked up to my 8" floppy? Or one of the Paper-Tape readers to load the hex on that ARM9? ;)

I'd like to get my hand on a paper-tape reader and writer again. I had one 30 years ago, but it was scrapped a long time ago (never throw anything away...). I'd hook it up to a RPI or PC and have an interactive system to do "something". Don't know what, but I probably can come up with a good plan :-)
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Re: Core-memory emulation design question

Postby Sleepwalker3 » Sat Aug 17, 2013 7:07 pm

Bertho wrote: I'd like to get my hand on a paper-tape reader and writer again. I had one 30 years ago, but it was scrapped a long time ago (never throw anything away...). I'd hook it up to a RPI or PC and have an interactive system to do "something". Don't know what, but I probably can come up with a good plan :-)


LOL, ok we'll see what we can work out ;) The problem isn't the reader, it's the tape and the punch, and I only have 1 roll left and only 1 punch left, so those would have to be sourced elsewhere unless you want to pay dearly for mine :D
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Re: Core-memory emulation design question

Postby blarson » Sun Aug 18, 2013 9:08 am

Has anybody done a program for a cell phone to read a paper tape pulled over a high-contrast backing yet? It shouldn't be to hard.
(Easier than OCR.)

The tape is just oiled paper, or sometimes mylar.
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