I've been thinking about BIOS and throughput, and revisited the (long) thread on vc-forum on the chuck-mod. Chuck himself has very kindly expanded on the design changes that would be needed to speed up writes via word instructions give 80188 or V20 CPU thus,
If I were to do a CPLD version, the change that would be required would be to take into account that the write signal to the IDE interface needs to occur on the output of the high-order byte, while when reading, the read signal occurs on the input of the low-order byte. Both IN AX,DX and OUT DX,AX transfer the low-order byte first, then the high-order byte.
Is this something we could have a go at with the CPLD code? The next XT-IDE universal BIOS (V2) is being developed actively it seems so maybe there could be scope to include changes for any new logic there, or at least fork that for it anyway.
As ever, any thoughts gratefully received!