Skip to main content
Topic: (EETimes) Using a Tiny FPGA (Read 2488 times) previous topic - next topic

(EETimes) Using a Tiny FPGA

Here is a URL to an article writeup for one of my projects (fragment):


[Maybe somebody can show me how to post a mixed page such as that here so it looks nice :]

If you don't want to go rooting around some web site I will attempt to summarize.

  I have programmed a Silego SLG44620 FPGA chip with both digital and analog elements for processing human interface devices (a rotary encoder with built-in push switch), plus measuring an ambient temp sensor to control a PWM variable-speed cooling fan.

  Part of the beauty of this device is that both the temp sensor and up/down counter are available totally asynchronously via a SPI device interface.  A rather simple piece of logic decodes the 2-bit Gray code (quadrature) from the rotary into DIRection and STEP pulses.  That means the 8-bit up/down counter gets 4 phase change pulses at STEP for each 'click' on the rotary.  Just read the register (the MSB half of the SPI) and shift right by two, which tends to deglitch the rotary and reduce sampling noise by 12dB.

  There is a simple clock-edge detector and inverter chain that deglitches the push switch.

  The analog section has a SAR ADC sampling a voltage divider that incorporates a 10K NTC thermistor for ambient air temperature.  The ADC digital out is shifted into a state register and copied into the LSB half of the SPI register.  Simultaneously the digital info is passed into a PWM unit for driving an external MOSFET which switches the PWM input of the cooling fan.  Normal room temperature (25C) results in approximate 30% duty cycle.  I can get it to 100% by touching the thermistor with a lighter flame.  If any piece of electronics get that hot in any case the failure is probably unrecoverable and the electrons tend to leak out.

  The end purpose of this project (fragment) is to set up the GUI menu selector for small follow-on controller projects (I am working on an A20-based controller).  The real winner is that all this processing eliminates two (maybe 3) ISR routines to poll out the hardware (plus having to have an external ADC since the A20 does not have one) and tying up more GPIO pins than I can really afford for GUI handling.

Re: (EETimes) Using a Tiny FPGA

Reply #1
Interesting project.

Had any trouble with testing the code? IIRC the chips are otp?

Re: (EETimes) Using a Tiny FPGA

Reply #2
There has not yet been any code to worry about.  Most brain rubs have been over the learning curve on the Silego part.  The controller board is still in layout and it has truly been a  bear.  This is my first try at DDR3 memory, and the CPU hasrequired me to "ride the beast that has 443 balls". The SDRAM only has 96 and that has been bad enough.

Re: (EETimes) Using a Tiny FPGA

Reply #3
I have revised the project a bit, with a MSP430 launchpad booster board implementation rather than the A20/DDR jazz (too hard for now and a bit of overkill :)  I have posted a schematic in the forum under "Red Board Blues".  I have also added a RDY output from the FPGA so that the processor does not read the SPI register "too soon", else the part goes into vapor lock.  The board has an 8-digit LED display, a connector for a smallish LCD panel, the temp devices, and an RTC - all on a 4-layer board that exactly matches the Launchpad dimensions.