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Ground for External Clock

I'm interested in using the OBLS to capture signals with a duration of between 5ns and 10ns as determined by an external clock from the circuit under test. In other words I'm using a "state machine" mode rather than a "timing mode" with a 100-200MHz clock.

As far as I can see from the schematic, the external clock input is only available on JP9. However, I can't see a nearby ground connection, so I'm concerned about the signal integrity of the external clock.

What's the recommended way of connecting an external 100/200MHz clock to the OBLS?

Thanks.

Re: Ground for External Clock

Reply #1 –
I would try using twisted pair or co-ax to carry the clock signal, but only ground the shield at the clock source.  Then a separate ground connection from the clock generator to the OBLS might be enough.

Re: Ground for External Clock

Reply #2 –
Thanks for the suggestion, but that would be equivalent to a very indirect ground connection. It would severely compromise the clock's signal integrity: I would expect to see very significant ringing!

The twisted-pair technique would probably be sufficient if and only if the twisted pair was "continued through" the clock connector JP9 to the ground plane. It might conceivably be sufficient to have the tp's ground going somewhere else and then have the signal wire glued to the board until it reaches the connector. I'd be prepared to try that if I had a 1GHz scope to see what the signal looked like -- but since that's what I'm thinking of making, I have a problem :)

Not having a ground for the external clock makes me wonder whether anybody uses the external clock input. Even at low clock rates, if the edge rates are normal then I would expect to see problems.

Anyway, thanks, and if anybody else has used the external clock input I'd be interested to know their experiences.

Re: Ground for External Clock

Reply #3 –
The clock cannot be more than 100Mhz.  The fpga can DDR sample off that to achieve 200Msamples/sec, but the core logic is limited to 100Mhz.

The lack of a ground header near CKI is a problem.  There are two capacitors off to the right though (C11 & C12).  You could solder a header pin there.  Not a perfect solution I know.

The fpga clock input needs to be clean, so you'll also likely need some type of termination.   
-- IED
-- debugging hardware at 2am is a bad idea...

Re: Ground for External Clock

Reply #4 –
Thanks dogsbody, that all seems sane.

I would probably ignore the connector and simply solder a twisted pair directly to the connector and capacitor as you describe.

I would also verify that the clock receiver was simply a single high impedance input connected pretty directly to the connector. Then if the twisted pair is approx 100ohms, I would have a have a 100ohm series resistor at the clock source. A half-height signal would propagate down the twisted pair and be 100% reflected at the receiver; the receiver at the end would only see a clean full-height transition.

Strikes me that when the board is revved it would be sensible to add two ground pins to the connector, one for the clock and one for the trigger.

Re: Ground for External Clock

Reply #5 –
[quote author="dogsbody"]Strikes me that when the board is revved it would be sensible to add two ground pins to the connector, one for the clock and one for the trigger.[/quote]
Yet another thing on the wish list. 

I'd also like to see a dedicated row of grounds next to the input header pins.  Would allow using shielded probe wires (like on the HP16550), and/or grounding off unused ports easily.    High impedance pulldowns on the headers would be nice (100K SIP's).  A DAC for programmable threshold voltages.  A larger fpga with external SDRAM, etc....  :-)

Alas, all unlikely...
-- IED
-- debugging hardware at 2am is a bad idea...

Re: Ground for External Clock

Reply #6 –
One of my mottos is
Quote
do one thing well, not two things badly

Hence I'd concentrate on ensuring the board functions without "suboptimal" surprises.

Thus:
  • do add the extra grounded header pins to allow shielded probe wires
but:
  • don't bother with 100K pulldowns. If floating pins are confusing the LA they will be confusing the UUT. If not then the LA isn't being used effectively (e.g. should be using the external clock to ignore pins when the value is irrelevant)
  • don't add the DAC. Programmable thresholds can be added externally -- and I'll be doing something similar for my requirements anyway!
  • don't add a larger FPGA and external memory: that's a different product
Get the fundamentals in place before adding bells and whistles!