Skip to main content ↑ ↓
Topic: urjtag and PROM to FPGA Configuration Mode (Read 4395 times) previous topic - next topic

urjtag and PROM to FPGA Configuration Mode

Hi all,

ok I guess all my other posts condense now down to this.
How to configure a PROM or FPGA via urjtag?

In Xilinx impact I can set different configuration options. However, those are NOT part of a generated SVF file.
They are included in the impact project file (ipf).

Just copy over the svf file is therefore not enough. One has to make sure PROM or FPGA are correctly configured.
How to do this within urjtag?

There is the instruction command and some other and I tried a bit around but couldn't see how this should work.

After solving this I guess I am ready to update the wiki ;)

Re: urjtag and PROM to FPGA Configuration Mode

Reply #1 –
Hey,

can't be that I am the only one who have to deal with that.
How do you configure, your PROMs and FPGAs?

Re: urjtag and PROM to FPGA Configuration Mode

Reply #2 –
Never had to configure them, just created the svf files and urjtajed them. Worked fine for me.

Maybe the problem is with the board? You mentioned that there are 2 FPGAs but only one was on the JTAG chain.

Re: urjtag and PROM to FPGA Configuration Mode

Reply #3 –
Hey,

ok i guess I got all parts together.
since a certain release impact has a function call "One step SVF". From there help

Quote
An SVF file named default.svf is created in your project directory. For PROMs and CPLDs, the SVF file contains device erase, program, and verify sequences using the specified configuration data file. For FPGAs, the SVF file contains a device program sequence using the specified device bitstream file.

Sounded good and valid to me. Erasing, Programming, Verifying... what else, right?!
Apparently NOOOOOO, thanks Xilinx!!!
This svf file does not contain any config option.
If you go the more complex way, creating a new project->Prepare a Boundary-Scan File (choose) SVF and do all the steps manually (really all, since they will be recorded ALL in the SVF file). It seems to work.
E.g., in the "hand-made" svf file, I found

Code: [Select]
//Operation: Program -p 0 -e -r -loadfpga -master -internalClk -clkFreq 20 -defaultVersion 0 
TIR 0 ;
HIR 0 ;
TDR 0 ;
HDR 0 ;
TIR 0 ;
HIR 0 ;
HDR 0 ;
TDR 0 ;
//Loading device with 'idcode' instruction.
SIR 16 TDI (00fe) ;
SDR 32 TDI (00000000) SMASK (ffffffff) TDO (f5058093) MASK (0fffffff) ;

The program operation was exactly what was missing within the "One step" SVF files. Thanks again Xilinx for making things more complicated!

I have now more or less a good overview of what to do and hope to update the wiki soon.
This is on the list at the moment:

* Using the busblaster with impact directly under Linux via the opensrouce drivers
* Creating valid SVF files from within impact
* Using urjtag and the busblaster under Linux
* Getting steppings and bsdl stuff right

I still want to check if I can manage to compile urjtag with the "native" ftdi_sio modules. That would avoid the usage and installation of the ftd2xx drivers and the necessary fiddling between those two modules.

Re: urjtag and PROM to FPGA Configuration Mode

Reply #4 –
Ok.... final feedback

libftdi module and urjtag are fine too.
That means we end up with those topics (all working)

* Using the busblaster with Xilinx impact directly under Linux via the opensource drivers (using a recent impact version 14.2)
Unclear here was whether the open source drivers still work with more recent versions of impact and the more recent kernel versions. There was another problem in case impact crashed or got killed. In that case sometimes the JTAG-cable was not longer recognized. It had to do with occupied semaphores which I could solve as well.
 
* Creating valid SVF files from within impact to be used by urjtag
The tricky part to create a SVF file which contains ALL necessary config steps.

* Using urjtag and the busblaster under (tested on Linux 64bit kernel 3.6.5) using the more common libftdi-module
Works under a recent Linux system, no need to use the proprietary FTDI drivers and hence no fiddling with unloading and loading modules resp. blacklisting them.

* Getting steppings and bsdl stuff right
Where to find and how to make use of bsdl files. How to get unkown steppings right.

Just need to find the time to update the wiki now. Help is welcome ;)

Re: urjtag and PROM to FPGA Configuration Mode

Reply #5 –
Wish I looked more into your project, was not aware that you were doing sth else.

I just do everything manually, so that's where our methods were different. Next time, you are showing your screen to me and I am busting your head with Sheldon like "WROOOONG!" screams. :D

Re: urjtag and PROM to FPGA Configuration Mode

Reply #6 –
Well the point is, there shouldn't be a point...

If this Xilinx people offer a "one-click" SVF generation... then they should do that right. It make no sens to leave the configure part out and I consider that actually a major bug.
Plus its even not enough to create manually a SVF file from an existing project, but to create a new project and assign directly a SVF file to it.

impact offers a batch mode as well, I guess it would be the best to figure out how to do all this in a batch file and hence avoid obstacles by pressing different buttons in different orders in a GUI.... grrrrrrr