Skip to main content ↑ ↓
Topic: urJTAG and XC5VLX50 and XCF16P (Read 10274 times) previous topic - next topic

urJTAG and XC5VLX50 and XCF16P

Hi all,

UPDATE: Please check the header changed slightly

I still struggel to get the toolchain up and running for the above device.
I got the Linux stuff working so far (at least I hope)
Here is a dump of what is working. I will be verbose to make sure I do not overlook something obvious

1. Temporary remove the standard ftdi drivers
Code: [Select]
rmmod lbftdi_sdio
2. start jtag
Quote
jtag
3. load cable drivers
Code: [Select]
jtag> cable jtagkey
Connected to libftd2xx driver.
4. call detect
Code: [Select]
jtag> detect
IR length: 26
Chain length: 2
Device Id: 01100010100010010110000010010011 (0x62896093)
  Manufacturer: Xilinx (0x093)
  Unknown part! (0010100010010110) (/usr/share/urjtag/xilinx/PARTS)
Device Id: 11100101000001011000000010010011 (0xE5058093)
  Manufacturer: Xilinx (0x093)
  Part(1):      xcf16p (0x5058)
  Stepping:     14
  Filename:     /usr/share/urjtag/xilinx/xcf16p/xcf16p
jtag>
As you can see there are two FPGAs onboard (a customer specific and a low-level routine one).
5. Select the recognized one
Code: [Select]
jtag> part 1
6. Check what print is giving me
Code: [Select]
jtag> print
 No. Manufacturer              Part                 Stepping Instruction          Register                        
-------------------------------------------------------------------------------------------------------------------
   1 Xilinx                    xcf16p               14       BYPASS               BYPASS                 


So far all looks good I guess.
I only have a MCS file from Xilinx ISE (no access to the sources yet). I called impact created a new project and importet the MCS file. I called the "One Step SVG" process which created a file default.svf

7. Call the SVF
Code: [Select]
  svf default.svf stop progress
Error svf: mismatch at position 31 for TDO
 in input file between line 21 col 1 and line 21 col 72
error: Error occurred for SVF command, line 20, column 0-71:
 SDR.
detail: Parsing 475240/475248 ( 99%)detail: 
detail: Mismatches occurred between scanned device output and expected TDO values.
jtag>

At this point I have trouble. Either the SVF conversion did not went right or something else is wrong as you can see from the output. The board does not react anymore (its not bricked I guess just not correctly programmed).

I would highly appreciate if someone can give me a hand and help me with that.

Two points I would like to notice.
The stepping for the FPGA was not available in urJTAG.
I manually added:
Code: [Select]
 1110    xcf16p  14
to  /usr/share/urjtag/xilinx/xcf16p/STEPPINGS

Also not sure why it selected xcf16p.

The second point. For impact I get asked during the project creation "Select PROM". I can select between
xcs1400an
xc3s700an
xcf16p
xcf32p

I used xcf16p since that is what urjtag was giving me... But still not sure about it.


Any help is welcome!

Re: urJTAG and XC5VLX30

Reply #1 –
Try loading BSDL files and then giving it a try.

Both problems can be related to that. Also while using impact, you have to put your jtag chain in the same order as detected order, and then create the svf file for the FPGA or PROM. It's been a while and I forgot some of the details but can pull out my fpga board on the weekend and try out some of the stuff.

Re: urJTAG and XC5VLX30

Reply #2 –
Hi Taylan,
thanks for responding.
As you can see from here

Quote
jtag> detect
IR length: 26
Chain length: 2
Device Id: 01100010100010010110000010010011 (0x62896093)
  Manufacturer: Xilinx (0x093)
  Unknown part! (0010100010010110) (/usr/share/urjtag/xilinx/PARTS)
Device Id: 11100101000001011000000010010011 (0xE5058093)
  Manufacturer: Xilinx (0x093)
  Part(1):      xcf16p (0x5058)
  Stepping:    14
  Filename:    /usr/share/urjtag/xilinx/xcf16p/xcf16p
jtag>

the second FPGA seems to be correctly identified. Anyhow I tried to load the BSDL file, the results are the same.
Still not sure I do the SVF conversion correctly in impact. I added a second device to mimick the chain as I found it by urJTAG as you said. Still receiving the same error messages.

I was going to try out to program directly from impact but the drivers trouble me. I have impact version 14.2 installed and it seems that the available drivers are not tested against this new version.
Will dig a bit more.

If someone has an detailed plan how to convert a MCS file into a SVF file I am eager to hear.

Re: urJTAG and XC5VLX30

Reply #3 –
The XCF16P is a Platform Flash chip: http://http://www.digikey.com/product-detail/en/XCF16PVOG48C/122-1456-5-ND/966637.

Looks like the FPGA still isn't being detected correctly.

I'm pretty sure there is a way to convert a .MCS file to a .SVF file. In iMPACT there should be an option to write a .SVF file instead of programming through a JTAG cable. Select that, then program the FPGA with a bitstream (or the Platform Flash with a .MCS file), then finish the .SVF file output (should be the same menu path as starting it).

Sorry, I don't have iMPACT handy to check the details. It's been a while since I tried this. :-)

Re: urJTAG and XC5VLX30

Reply #4 –
[quote author="torwag"]the second FPGA seems to be correctly identified. Anyhow I tried to load the BSDL file, the results are the same.
Still not sure I do the SVF conversion correctly in impact. I added a second device to mimick the chain as I found it by urJTAG as you said. Still receiving the same error messages.[/quote]
In iMPACT you can create two SVF files: One for the FPGA, the other for the PROM. With the FPGA file, you can only program the FPGA and if you remove the power after programming, you'll lose the program in there. With the PROM file, you can only program the PROM, then you have to reset the board, so that the FPGA can load the configuration. Good thing is the configuration is still there after the power loss.

Burned through this weekend working on a paper. I'll take my FPGA stuff with me to write detailed instructions about how I used iMPACT and urJTAG.

Re: urJTAG and XC5VLX30

Reply #5 –
ok I make little progress. Still not there but it seems to get better.

First of all apologize I mixed up a few things

The board HAS two FPGAs on board. However, the JTAG chain is only connected to one of them and to its platform flash (thanks dps). That confused me first since I expected to see both FPGAs.

Furthermore, I learned that urJTAG fails if not really all devices in the JTAG chain are recognized by urJTAG.
I believe this has something to do with the fact that impact addresses the devices from within the SVF-file whereas urJTAG has the part commando. Having an unkown (even bypassed) device in the chain resulted in error messages reading the SVF file from within urJTAG.

I copied over BOTH bsdl files from the xilinx webpack installation and pointed urJTAG to them.
In total just for the record (and maybe someone will like to read this during his own struggle with this stuff...)
After starting urjtag (again by calling jtag not urjtag ;) )
Code: [Select]
jtag> cable jtagkey
Point urjtag to the folder where you keep the bsdl files
Code: [Select]
jtag> bsdl ./bsdl
see whats recognized now!
Code: [Select]
jtag>detect
IR length: 26
Chain length: 2
Device Id: 01100010100010010110000010010011 (0x62896093)
  Filename:     ./bsdl//xc5vlx50_ff1153.bsd
Device Id: 11100101000001011000000010010011 (0xE5058093)
  Filename:     ./bsdl//xcf16p_fs48.bsd
Hurray... all are there.
Call svf to flash the svf-file
Code: [Select]
jtag> svf default.svf progress stop
warning: command HIR not implemented
warning: command HDR not implemented
warning: command HIR not implemented
warning: command HDR not implemented
detail: Parsing 475240/475249 ( 99%)warning: command HIR not implemented
warning: command HDR not implemented
error: Error svf: SIR command length inconsistent.
error:  in input file between line 475249 col 1 and line 475249 col 41
error: Error occurred for SVF command, line 475248, column 0-40:
 SIR.
detail: Parsing 475250/475249 (100%)detail: 
detail: Scanned device output matched expected TDO values.

Ok thats looks better already. However, the warnings and one error remain.
Board is still not working....

From what I read on the urjtag mailing list this might be a problem. Having two devices in a chain might require some way of implementing the HIR and HDR comands to work correctly.

Any help is greatly welcome.
Did someone here already use mutliple devices in a JTAG chain in combination with urjtag and the busblaster?

Any more ideas?

Thanks

Re: urJTAG and XC5VLX30

Reply #6 –
[quote author="torwag"]Did someone here already use mutliple devices in a JTAG chain in combination with urjtag and the busblaster?[/quote]
I have. Same system as you: An FPGA + PROM combo.

Just a question: How do you create your svf file? You have to create the exact JTAG chain in impact + select the device to create the svf for. As I recall:
[quote author="tayken"]
In iMPACT you can create two SVF files: One for the FPGA, the other for the PROM. With the FPGA file, you can only program the FPGA and if you remove the power after programming, you'll lose the program in there. With the PROM file, you can only program the PROM, then you have to reset the board, so that the FPGA can load the configuration. Good thing is the configuration is still there after the power loss.[/quote]

Re: urJTAG and XC5VLX30

Reply #7 –
Ok guys I am making little steps forward here.
After a nice night-IRC chat with Tayken we get closer...
Status now:

Can use Xilinx impact + the open source Linux drivers + busblaster to burn both PROM and FPGA. This works !!!! but is slow like hell.
I CAN'T for some strange reason burn an svf file by urjtag. I tried in different ways to convert the MCS file into a SVF file by using impact.
1. Using impact boundary scan and assigning the MCS-file to the PROM, convert this to a SVF, using urjtag to flash->fails
I thought it might fail because urjtag can't deal with multiple device info in the SVF file (warnings and errors in urjtag).
2. Created a single device (PROM) by hand and assigned the MCS-file to it, convert to an SVF file, using urjtag to flash->fails
This time urjtag does not brag about any warnings or errors. Thus leaving me clueless what is going wrong. The SVF file should be the exact copy of what impact would do if it would directly write via a cable.

At the moment I try to read-back the PROM after flashing it with urjtag (which renders the board non-function). Lets see if this gives some idea what went wrong using urjtag.

Some side remarks.
During start-up of the svf flash command in urjtag takes rather long about a minute before the progress bar appears. In that time urjtag takes as little as 1.5GB of the PC RAM. A bit greedy if you ask me... noticed that when swapping kicked in and my Linux-box got as slow as running the same machine under Windows ;).

Ahh if you flash PROM or FPGA via impact, do not trust the progress bars. Silly me who thought that programming and verification would split the progress into half... noooooo programming takes from 0 to 99% and then you stuck for another 15-20 min on the last percent for verification. But hey Xilinx never claimed a linear progress bar... I guess this is an upcoming feature for Webpack 15 or the paid version :)

Re: urJTAG and XC5VLX50 and XCF16P

Reply #8 –
Ok here it continues...

I read back the the PROM content written by urjtag.
The files are almost identical beside of the very last line.
The original file contains nothing at the end the read-back file (read-back was done by impact) contains ^M at the very end.
I would assume that might be a problem of impact, since the MCS format does not deal with any special characters.

Thus, I could assume that the content of the PROM and the original file is equal.

I somehow have the impression that the PROM is not correctly configured using urjtag.
In impact I can tell via the programming parameters which clocks are used and whether the PROM should load the FPGA.
Esp. this flag seems to be interesting.

Xilinx helps says:

Load FPGA
Sets the Load FPGA flag in XC18V00 or Platform Flash PROM device. When this option is set, once the PROM is configured the PROM toggles the FPGA's program pin and configuration commences automatically.

Activated this I can flash the PROM via impact and it works. However, using the same impact project to generate a SVF file and trying to use urjtag does NOT work. The question is, does the SVF file contains those programming settings?

Lets make a diff.... will be back soon ;)

Re: urJTAG and XC5VLX50 and XCF16P

Reply #9 –
ok I checked the SVF file for different programming settings.
They are both identical. That means the programming settings as you can reach from within impact are NOT part of the SVF file.
Now I leave with the question how to set those programming flags from within urjtag.
Couldn't find any info yet.

The info is saved in the impact project file (.ipf) but how to get it from there into the jtag chain via urjtag?

Re: urJTAG and XC5VLX50 and XCF16P

Reply #10 –
Quote
The info is saved in the impact project file (.ipf) but how to get it from there into the jtag chain via urjtag?

Did you make any progress on this? You've advanced well beyond my abilities with this tool chain, I'm not sure what the next step is.
Got a question? Please ask in the forum for the fastest answers.

Re: urJTAG and XC5VLX50 and XCF16P

Reply #11 –
Yep, he solved it. :)

The problem was this: He was using automatic SVF creation process, I was doing it manually. If you do it manually, config info gets stored in SVF file.