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Topic: Bus Blaster & Actel FPGAs (Read 15838 times) previous topic - next topic

Bus Blaster & Actel FPGAs

Hi! I would like to know if i can use the Bus Blaster in combination with the Actel ProASIC3 (A3P125)

Thank you!

(Sorry for my poor english)

Re: Bus Blaster & Actel FPGAs

Reply #1 –
Nobody can answer me?

Re: Bus Blaster & Actel FPGAs

Reply #2 –
It depends on the software more than the chip. If your programming software supports any FT2232-based programmers then it should work. Common types are KT-link, JTAGkey, and just FT2232. I'm not familiar with this chip or what IDE you are using, so it is difficult to say for certain.
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Re: Bus Blaster & Actel FPGAs

Reply #3 –
[quote author="mk2soldier"]Nobody can answer me?[/quote]

If your programming files are in SVF format, then you can use urjtag. In such case, you can just download the BSDL file corresponding to your FPGA and you should be fine...

On the other hand, if your programming file is in DAT format, then you can use my FT2232-based version of the Actel's DirectC 2.7 programming utility, which I made compatible with the Bus Blaster. I have extensively used it to program different FPGAs and works fine. I'm attaching the Linux x32 executable just in case you're interested in using it (you will also need to install libusb-1.0). I'm not releasing the sources yet since the code is a bit messy.

Re: Bus Blaster & Actel FPGAs

Reply #4 –
Thanks for sharing mikelelere, nice work. Please let us know when you post the source, I'll link it in the documentation.
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Re: Bus Blaster & Actel FPGAs

Reply #5 –
Cool. I was working on programmer using their Direct C utility, but that was before the Bus Blaster. I would also be interested in the source.

Re: Bus Blaster & Actel FPGAs

Reply #6 –
Anyone wants some good news?

Here we go.

Mikelelere's linux binary is damn slow, 30mn to program an a3p125.

I made some modifications to that tool, and now it can program my devices in about 3mn (three minutes!)

osx, linux, win32, and source code to come. stay tuned.

Re: Bus Blaster & Actel FPGAs

Reply #7 –
[quote author="elbeem"]Anyone wants some good news?

Here we go.

Mikelelere's linux binary is damn slow, 30mn to program an a3p125.

I made some modifications to that tool, and now it can program my devices in about 3mn (three minutes!)

osx, linux, win32, and source code to come. stay tuned.[/quote]

Good news. Do you need beta testing? I have one A3P250 board lying around.

Re: Bus Blaster & Actel FPGAs

Reply #8 –
Any update here? This sounds great!
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Re: Bus Blaster & Actel FPGAs

Reply #9 –
here is the source code.

Linux: just type make
OSX: just type make
Win32: sorry, minor edits to do (usleep, libusb includes, driver, ...). So far, i was able to compile it with cygwin (source code not uptodate), but i'm stuck at running it (shitty, shitty, shitty windows driver management). feel free to do it!

also, lots of supported platform were removed, but it's very easy to add new ones, just by inputting new vid/pid in dpuser.c

the real hack to speed it up was to buffer output bytes before sending them. i've packed them by 50, it's ugly but it works.

all this shit was done during 29c3, in an agitated, warm, noisy environment.

it was also tested on flashing an igloo agl250 (that was the test i wanted to get before publishing it) in 6m22.

Re: Bus Blaster & Actel FPGAs

Reply #10 –
here are osx (mach-o 64)  & linux (x86) binaries

Re: Bus Blaster & Actel FPGAs

Reply #11 –
Sorry about the double post. Damn tablets!

Re: Bus Blaster & Actel FPGAs

Reply #12 –
[quote author="bmx"]
the real hack to speed it up was to buffer output bytes before sending them. i've packed them by 50, it's ugly but it works.
[/quote]
Buffering is obviously a solution to improve speed, but note that Actel's utility is designed as a bitbanged async JTAG programming software, and as such, the intended TDI waveform is modeled using delays. Therefore, to achieve a perfect TDI signal (neglecting the USB overhead), you need to implement the actual signal durations by inserting dummy writes when buffering the data based on the selected clock speed. This is not necessary when not using buffering, since there are calls to the mdelay function all over the code.  I've not checked your code in depth, but I think that you're not respecting these timings in your code. Timing does not seem to be critical given your results, but be aware that the input signal you're providing to the FPGA is not the expected one, and thus, unexpected failures may occur (unnecesarily wasting flash write cycles, which are quite limited in these FPGAs). That's why I did not follow a buffered approach. I'd rather being safer than quicker ;-)

[quote author="bmx"]
also, lots of supported platform were removed, but it's very easy to add new ones, just by inputting new vid/pid in dpuser.c
[/quote]
This is true for raw FT2232H devices or JTAGKEY compatible-devices, but it is not for other platforms including any buffer logic (such as the Bus Blaster equipped with a different buffer). In such case, it would also be necessary manually enabling the required buffers.

There's even a much better and faster way to carry out this task. As you may have noticed, I've used MPSSE GPIO to implement the async bitbanged interface, but the MPSSE also offers sync JTAG commands which in addition hugely facilitate buffering. You only need to adjust the clock speed (and insert dummy writes when required) and you're ready to go! I would have followed this approach, but unfortunately I'm too busy and lazy for that ;-) This is the main reason why I did not yet release the code...

I'm fairly surprised about the quality of the decompiled code. I know that the symbol table was there (I always leave it there for debugging), but... which tool did u use to reverse the code?

Cheers

M.

Re: Bus Blaster & Actel FPGAs

Reply #13 –
Thank you all!