spartan/virtex 6 + ddr2/3 ?

Topic: spartan/virtex 6 + ddr2/3 ? (Read 41499 times) previous topic - next topic

Re: spartan/virtex 6 + ddr2/3 ?

Reply #15 – July 17, 2012, 10:26:24 pm

[quote author="Nexus"]Jack is working on a spartan 6 Papilio board with sdram[/quote]

184pin ddr1 sticks? that would be superb :D

Re: spartan/virtex 6 + ddr2/3 ?

Reply #16 – July 17, 2012, 11:08:06 pm

[font=Georgia:]criteria

Suppose you want a common high-performance hardware platform for a variety of projects. You might consider a common daughter-board that plugs into a variety of easy-to-design two-layer project-specific motherboards (which only have connectors, buffers, phys, power supplies, etc.). In this case, you might design a daughter-board with the following features:

The Xilinx Zynq 70x0 series were announced a couple years ago, but Xilinx only just started shipping silicon.
These parts are complicated products to develop. They will take awhile to come down in price, but that will happen. If only because Altera is designing competing products.

Thanks for your time.

dsm[/font:]

Re: spartan/virtex 6 + ddr2/3 ?

Reply #17 – July 18, 2012, 01:27:42 am

[font=Georgia:]Xilinx FPGA packaging

The following information is from the Xilinx site (link).

First pass screen ~ non-BGA packaging

Spartan-3E ~ DS312-1 ~ some
Spartan-3A ~ DS529-1 ~ some
Spartan-3AN ~ DS557 ~ some
Spartan-3A DSP ~ DS610 ~ BGA only
Virtex-4 ~ DS112 ~ BGA only
Virtex-4Q ~ DS595 ~ BGA only ~ defense-grade => $$$$
Virtex-4QV ~ DS653 ~ BGA only ~ space-grade => $$$$
Virtex-5 ~ DS100 ~ BGA only
Virtex-5Q ~ DS174 ~ BGA only ~ defense-grade => $$$$
Virtex-5QV ~ DS192 ~ BGA only ~ space-grade => $$$$
Viirtex-6 ~ DS150 ~ BGA only
Virtex-6Q ~ DS155 ~ BGA only ~ defense-grade => $$$$
Spartan-6 ~ DS160 ~ some
Spartan-6Q ~ DS172 ~ BGA only ~ defense-grade => $$$$
Virtex-7 ~ DS180 ~ BGA only
Zynq-7 ~ DS190 ~ BGA only
[/list]
Second pass screen ~ number of package pins (user IOs)

Just for reference, both the OBLS and the Papilio One 250K designs appear to use the
Xilinx Spartan-3E XC3S250E-VQG100-4C device, while the Papilio One 500K design appears to use the
Xilinx Spartan-3E XC3S500E-VQG100-4C device.

[hr:][/hr:]
[quote author="arhi"]184pin ddr1 sticks? that would be superb :D[/quote]
About one quarter of the pins on a 184-pin DIMM are either power or ground.
Of the remaining pins, 72 are either data or parity/ECC.
That leaves roughly 66 control or NC pins.
I suspect that it's hard to effectively support 184-pin DIMMs with non-BGA FPGAs.

Thanks for your time.

dsm

[hr:][/hr:]
[quote author="nexus"]Jack is working on a spartan 6 Papilio board with sdram[/quote]
The Papilio Plus design (link) appears to use the Xilinx Spartan-6 XC6SLX9-TQG144 [1] device with

The Papilio Pro design (link) also appears to use the Xilinx Spartan-6 XC6SLX9-TQG144 [1] device with

[1] Xilinx (link) ~ speed/temperature range undetermined
[2] ISSI (link) IS61WV25616BLL (link) 16x256K (4Mb) SRAM or Cypress (link) CY7C1041D (link) 16x256K (4Mb) SRAM
[3] Micron (link) MT48LC16M16A2 (link) 16x16M SDRAM
[4] 40-pin memory interface (16 data + 19 addr + 5 ctl) out of 102 user IO pins
[5] 39-pin memory interface (16 data + 13 addr + 10 ctl) out of 102 user IO pins

Thanks for your time.

dsm[/font:]

Re: spartan/virtex 6 + ddr2/3 ?

Reply #18 – July 18, 2012, 10:47:58 am

Even if you have enough pins to interface the SDRAM to a Spartan 6 tqfp 144, and the ft2232, you are still left with the problem of designing the memory lines on a 2 sided board..

Re: spartan/virtex 6 + ddr2/3 ?

Reply #19 – July 18, 2012, 10:50:20 am

[quote author="dsm"]
Just for reference, both the OBLS and the Papilio One 500K designs appear to use the
Xilinx Spartan-3E XC3S250E-VQG100-4C device.[/quote]

Papilio one 500k uses the xc3s500e hence the name papilio one 500k :)

Re: spartan/virtex 6 + ddr2/3 ?

Reply #20 – July 18, 2012, 11:02:35 am

[font=Georgia:]Oops!

[quote author="arakis"]Papilio one 500k uses the xc3s500e hence the name papilio one 500k :)[/quote]
Sigh... Serves me right for not proofreading closely enough. Corrected above.

Thanks for your time.

dsm[/font:]

Re: spartan/virtex 6 + ddr2/3 ?

Reply #21 – July 20, 2012, 10:05:57 pm

[quote author="arhi"]That's why I asked if DP is designing a new board :D. If I could find a good chip in 208 tqfp I'd try to do it myself (not sure 208 is enough for ddr2 also, they are 72pin modules iirc)[/quote]
Just a teaser:

Check out Spartan-3 and Spartan-3E in 208 pin PQFP package:
- XA3S200 (PQG208) - max. 141 user I/O
- XA3S400 (PQG208) - max. 141 user I/O
- XA3S250E (PQG208) - max. 158 user I/O
- XA3S500E (PQG208) - max. 158 user I/O

No real performance gain with those Spartan-3/3E devices compared to the OBLS ver. 1, so!
... and sourcing the devices in the 208-pin QFP package may turn into a real head banger ;)

I wouldn't discard Zynq-7000 EPP right from the start ... the dual-core Cortex-M9
on the chip may have some real value ... --> Free webinar: FPGA programming in C code

Off topic ... not really (since I read some comments on the blog entry for the webinar
- not the ones about webinars in general as I am no fan of live webinars myself):
Some people were laughing when Miro Samek published his book Practical State Charts in C/C++!
I loved the idea right from the moment I read the headline since I had been using C to
convert state charts/diagrams and generate fusemaps for ROMs and PALs (the first
commonly available PLDs to implement state machines) long before the book had
been published! However, it took me to read the title of the book to understand
that state machines are perfect to implement solid, determined and very efficient
code for MCUs. Since then I have used this approach for bare metal coding many times.

Getting back on subject, there are some real benefits in splitting tasks between MCUs
and logic/gates both residing on the same chip in particular if there is a need to change
between different functions/state machines that would take up more logic footprint or
paths than the FPGA can provide but are not very time critical ... the combination of MCU
and logic array allows the design of "dynamic" logic (vs reloading the FPGAs configuration)
... a feature that comes in rather handy e.g. for reactive pattern and waveform generators etc.

Regardless, Zynq-7000 are no good choice if the design requirements exclude any
components that can not be assembled by hand (BGAs etc).

Re: spartan/virtex 6 + ddr2/3 ?

Reply #22 – July 21, 2012, 03:46:04 am

[quote author="IPenguin"]
Check out Spartan-3 and Spartan-3E in 208 pin PQFP package:
- XA3S200 (PQG208) - max. 141 user I/O
- XA3S400 (PQG208) - max. 141 user I/O
- XA3S250E (PQG208) - max. 158 user I/O
- XA3S500E (PQG208) - max. 158 user I/O
[/quote]

I did, what I wanted to do they can't handle ... I will try to make logic analyzer work with XC3S700AN-FG484 + 32M x 16 DDR2 SDRAM that I have on HW-SPAR3AN-SK-UNI-G dev kit, but it's mostly for learning purposes only, that's not enough ram for what I want nor I think that is fast enough for what I want... also I wanted to be able to do some additional stuff ..

Quote

Regardless, Zynq-7000 are no good choice if the design requirements exclude any
components that can not be assembled by hand (BGAs etc).

unfortunately BGA is a huge issue for me hence I forgot about it... I spent 4 hours during zynq announcement locally, another 4 hours on some zynq presentation, also locally .. love the idea, the price they mentioned then - loved that too, everything but the package ...

Re: spartan/virtex 6 + ddr2/3 ?

Reply #23 – July 21, 2012, 08:08:07 am

Maybe it's time for a simple high-precision Mini-PnP project bare auto-feeding.
One that can place single BGA packages, narrow pitch QFPs ... essentially every
SMD component step by step even if it requires swapping the grabs/stamps
(tools) by hand ... for prototype and small batch assembly. We need to keep up
with advancing packaging and assembly technologies :)

... I know, at some point 2-layer PCBs won't do anymore :(

Re: spartan/virtex 6 + ddr2/3 ?

Reply #24 – July 21, 2012, 08:32:05 am

[quote author="IPenguin"]Maybe it's time for a simple high-precision Mini-PnP project bare auto-feeding.
One that can place single BGA packages, narrow pitch QFPs ... [/quote]

I was thinking about that a lot and gave up. The system for picking and placing a chip would not be too problematic as even with cheap aluminium frame and some nema17 400 steps per revolution, some belts (as they have way less backlash then anything else) and a cheap 1/16 stepper driver we can get easily micron precision in positioning. Problem is that ability to move head precisely ain't the solution :( as coordinates depend on the origin and setting origin is almost impossible to do precise using mechanic. I went searching for how real machines do it and it's all optical, some do it automatically, most do it "with human assistance" but they all navigate the board using optical markers. Then I checked out the "soldering system's" for bga repair as that's similar to what we need, they again use visual tools to position chip properly ... you don't even need motors, 2 levers are with good gearing as you do not need to place 200 chips, only one or two ..

Anyhow, I found that I do not have that much troubles "placing" the chip, and as we all know the surface tension will fix slight mistakes we make, the problem is soldering the sucker. I god some "broken" bga chips (small bag of them, some asic chips with defect) from a friend and I made a simple 2 sided board with a via for each pin and then I tested the connections of the chip (chips work, it's the logic in chip that was broken, not the chips themselves) ... what happened is that using simple reflow oven, heat gun and soldering via's one by one with soldering iron - NOT A SINGLE CHIP had all pins soldered to the pcb :( and I think I tested 30 or 40 of them .. (all I got) .. and there was no rule I could get about what pins don't solder properly, sometimes those in the middle, sometimes ones on the edge ..

What I concluded is that BGA present 3 problems
1. positioning - solvable
2. soldering - I was unable to solve (maybe with a reflow oven with proper heat profile..)
3. routing - anything with more then 16 pins becomes unroutable on the 2 sided board + most of the chips have number of power pins that all need to be connected and that draw a lot of current so routing 3mil traces between bga pins to them ain't going to cut it .. you need at least 2 power layers if not some signal layers apart from the top and bottom one ...]

1+2+3 = I gave up on bga, now let's see if GF can make affordable papilio board with spartan6 ... I hoped DP would venture into making obls v2 with spartan 6 as seeed can probably get them some test batches cheaper then we, ordinary ppl, can do them but looks like it's not going to happen (as I see most development is now on the part ninja and that "secret" project that looks like some kind of arduino shield, and I don't believe there's a valid reason to connect spartan 6 logic analyzer to arduino :D so that project is obviously something else, hopefully we'll soon know what it is :D and hopefully it's another success by DP - keeping fingers crossed)... from what I read so far GF has a lot of experience with spartans .. (lot more then I do for sure), I just hope he add some standard ram connector on his boards and get them affordable ..

Re: spartan/virtex 6 + ddr2/3 ?

Reply #25 – July 23, 2012, 05:30:46 am

@arhi: Thanks for sharing your BGA soldering experiments/experience. Sorry to hear that you did not have any success despite all your efforts. I agree with your conclusions:

1. Yes, surface tension will fix slight misplacements. :)

2. Since surface tension corrects misalignment (torsion/yaw) to a lesser degree than misplacement
a simple but via optical guidance precise PnP could reduce assembly time and help to reduce "duds".

3. For various reasons there is no other (affortable) way but to use a reflow oven and solder with the specified ramp up profile. (actually the vias in the (center?) of the pads may have caused the issues ... because they may have disrupted the surface tension ... I am not sure if I understand your the configuration of the pad/via configuration correctly, so).

4. If you go BGA you have to go 6 layers unless it's a real small/simple package, e.g. only one or two pin rows.

Anyway, assembling BGA designs is a more general subject. Not sure if there is much interest for it among members of the DP community.

Since O(B)LS started out with a SUMP implementation on GFs Butterfly board (predecessor of Papilio) the next generation Papilio with Spartan 6 should make for a good platform for those who may need more performance/features than the OBLS can offer.

Re: spartan/virtex 6 + ddr2/3 ?

Reply #26 – July 23, 2012, 05:46:26 am

[font=Georgia:]Multi-layer Board Design and Fabrication Issue

[quote author="arakis"]Even if you have enough pins to interface the SDRAM to a Spartan 6 tqfp 144, and the ft2232, you are still left with the problem of designing the memory lines on a 2 sided board..[/quote]
I suspect that you're right about using a two-layer board, but PCB layout tools that can handle multi-layer boards are readily available. For example, KiCad.org KiCad (link) is probably capable enough to handle board designs with dense routing. I also don't think open source hardware should only be limited to freeware [1] PCB layout tools. For example, Altium Designer can be rented on a month-by-month basis at a low cost.

[quote author="arhi"]
it's probably going to require 4 layer board, bga chip .. so might be a perfect opportunity to switch from eagle to kicad :D (or design the thing in Altium or Cadence and then redraw in kicad/eagle)[/quote]
I suspect six-layer [2] or eight-layer [3] boards might be needed for many designs with leading edge components.

[hr:][/hr:]
Boards with BGAs Assembly Issue

[quote author="arhi"]What I concluded is that BGA present 3 problems
1. positioning - solvable
2. soldering - I was unable to solve (maybe with a reflow oven with proper heat profile..)
3. routing - anything with more then 16 pins becomes unroutable on the 2 sided board + most of the chips have number of power pins that all need to be connected and that draw a lot of current so routing 3mil traces between bga pins to them ain't going to cut it .. you need at least 2 power layers if not some signal layers apart from the top and bottom one ...]

1+2+3 = I gave up on bga[/quote]
[quote author="IPenguin"]We need to keep up with advancing packaging and assembly technologies :)[/quote]
[quote author="IPenguin"]Maybe it's time for a simple high-precision Mini-PnP project bare auto-feeding.
One that can place single BGA packages...[/quote]
I once proposed an improved imaging processing architecture for an X-ray machine intended to automatically inspect dense boards with BGAs for soldering defects at the beat-rate of a PCB assembly line. One of my personal lessons from this exercise was that I was quite happy to let professional assembly operations assemble my boards that needed BGAs. Companies have made large investments for equipment and do an amazingly good job performing board assembly for remarkably little money.

< rant on >

Am I the only one willing to let a professional assembly operation build dense boards with BGAs for me?

I like designing stuff (which pays relatively well), but I am more than willing to let someone else assemble my boards (which pays relatively poorly). Further, if my designs are successful, the designs will have to be move to a professional assembly operation anyway. Economic "comparative advantage" arguments aside, designing stuff and programming stuff is generally more fun than applying paste, positioning parts, and running a reflow oven to assemble stuff.

The SO-DIMM board with a Xilinx Zynq-70x0 BGA described previously in this forum thread could be professionally assembled and tested. This processor-memory-FPGA hardware haiku could then be plugged into relatively simple motherboards that you would be able to design and build in your home lab.

We use parts every day that we could not build by ourselves. For example, given that there are multiple companies that will build multi-layer boards for me at a reasonable cost, I no longer build my boards in my bathtub. Given that there are companies that build 7400 quad-nand-gate devices (and other other rumored devices of even greater complexity), I no longer build computers out of transistors, resistors, diodes, switches, and miniature incandescent bulbs. Interesting FPGAs in BGA packages are just the latest example.

< rant off >

Thanks for your time.

dsm

[1] The freeware version of CadSoft Eagle (link) is limited to

[2] four wiring layers, two power layers

[3] two outside ground layers (for lower emissions), four wiring layers, two power layers[/font:]

Re: spartan/virtex 6 + ddr2/3 ?

Reply #27 – July 23, 2012, 06:29:36 am

[quote author="dsm"]PCB layout tools that can handle multi-layer boards are readily available. [/quote]

Tools are not the problem, in the worse case you can steal them from torrent, in the best case you can use some free open source one with some external scripts to help calculate impedance, length etc etc but have you looked at the prices of multilayer boards? You have to go to professional manufacturing to get 6 layers... Look at seeed/itead, they offer 4 layer that's unusable for bga (no blind nor buried vias are supported and you need both for bga and even that is $65 for 5x5cm board), we'r talking more then $100 for a board the size of OBLS at 100+ quantity (and you are lucky if they want to go with only 100 pcb's that small at all), that's $10000 investment only for the pcb... It's something a company that's going to be selling those can afford but a hobbyist can only laugh to it .. You can get deep memory 256 channel logic analyzer for few hundred bucks on ebay ..

Re: spartan/virtex 6 + ddr2/3 ?

Reply #28 – July 23, 2012, 06:58:46 am

Here is a memory-Spartan-6 haiku - Trenz Electronic TE0630 Series
... a "little" short on memory/width for what you are looking for (it's only 128MB/16-bit) :P
Don't check the price ;)

Re: spartan/virtex 6 + ddr2/3 ?

Reply #29 – July 23, 2012, 08:38:05 am

330EUR .. and they say "competitive price" .. :(
on the other hand they do use $160 fpga on there so it's maybe not "too much" but ..