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Topic: Bus Blaster v4 power up test success, bitstream next (Read 50434 times) previous topic - next topic

Re: Bus Blaster v4 power up test success, bitstream next

Reply #15
Hello,

I got a Bus Blaster v4 from the Free PCB drawer. I have soldered it together, and I *think* I have successfully programmed the CPLD.

I wasn't able to find a BBv4 bitstream, so I edited the jtagkey buffer ucf file to match the new XC2C64A VQ100 pinout and generated a new SVF file.

I installed UrJTAG 0.10 #2024 from SVN and was able to get it to compile on OS X using
Code: [Select]
./autogen.sh --disable-werror
Next I googled around for a XC2C64a bsdl file; http://http://bsdl.info/view.htm?sid=bf5910466c75c02088ca59b002289d77

and followed the instructions on the http://http://dangerousprototypes.com/docs/Bus_Blaster_v2_manufacturing_resources

The next step seems to be getting the self test to work.

Re: Bus Blaster v4 power up test success, bitstream next

Reply #16
Is there an ISE project for the BBv4 Self test buffer?

With my modified version of the BBv2 jtagkey buffer, UrJTAG does recognize both CPLDs on my old Digilent XC2-XL dev board.

Code: [Select]
jtag> cable jtagkey interface=0
Connected to libftd2xx driver.
jtag> detect
IR length: 16
Chain length: 2
Device Id: 01001001011000000100000010010011 (0x49604093)
  Manufacturer: Xilinx (0x093)
  Part(0):      xc9572xl (0x9604)
  Stepping:    4
  Filename:    /usr/local/share/urjtag/xilinx/xc9572xl/xc9572xl_cs48
Device Id: 00000110110101001100000010010011 (0x06D4C093)
  Manufacturer: Xilinx (0x093)
  Part(1):      XC2C256-TQ144 (0x6D4C)
  Stepping:    0
  Filename:    /usr/local/share/urjtag/xilinx/xc2c256-tq144/xc2c256-tq144

Re: Bus Blaster v4 power up test success, bitstream next

Reply #17
Hi skoot9000,

Fantastic news, thank you for sharing. Would you be willing to contribute the modified .ucf file for BBv4?

As far as I know there is no bitstream project at all for BBv4 yet, I had planned to do the self test buffer first because it's the one we use in manufacturing.
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Re: Bus Blaster v4 power up test success, bitstream next

Reply #18
Sure.

I haven't done a lot of testing with it, but UrJtag seems to recognize connected CPLDs fine.
I couldn't figure out what to do with "TARGET_PRESENT" input so I hardcoded the "FT_TARGET_PRESENT" output to 0 in the verilog.

here is my UCF file and the SVF file I generated.
[attachment=0]

I guess I meant; Is there a BBv2 Self-test ISE project I can look at to modify into one for BBv4?

Re: Bus Blaster v4 power up test success, bitstream next

Reply #19
Hey Skot,

Thanks for the UCF. The self-test buffer wasn't actually in SVN for some reason, so I checked it in at the beginning of the month with an updated ucf for the v3 Bus Blaster. I'm sorry,It looks like I forgot to reply here.

Here's the self-test jtagkey buffer with ISE projects for v2 and v3:
http://code.google.com/p/dangerous-prot ... AGkey_test

I'm going take a look at what needs to be added to the v4 UCF to get it going with the self-test buffer.
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Re: Bus Blaster v4 power up test success, bitstream next

Reply #20
It looks like we removed target_present from v4. Wiring either way is probably ok, I don't think many programs rely on it.

I added your ucf to the test mode buffer folder in SVN. I made a few tiny changes:

Code: [Select]
NET "FT_DBGACK"         BUFG = CLK;  #AC5 is clock out in 485 mode

because FTDBGACK is clock out for a potential 60MSPS logic analyzer mode and we did make the effort to route it to a GSK pin :)
Code: [Select]
//control pins for test mode
input wire TEST_MODE_0; //has pullup, pull low to ground to enter test mode
inout wire TEST_MODE_1; //outputs high (light LED) on test mode active
wire TEST_MODE;

There are 2 new signals and pins used by the test buffer, Test_MODE_0 and TEST_MODE_1. There is a TEST_MODE_2 too, but it is unused and should be removed (I may check in one with it removed now).

Code: [Select]
#trigger pins for test mode
NET "TEST_MODE_0"    LOC =  "P1"; #test mode trigger pin, pull low to enter test mode
NET "TEST_MODE_0"    PULLUP;
NET "TEST_MODE_1"    LOC =  "P64"; #test mode output pin, usually the LED
NET "TEST_MODE_1"    PULLUP;

I added them to the v4 UCF and assigned the trigger pin to P1, short it to ground to enter test mode. (Make sure the on-board power jumper JP4 is closed to power the front end with 3.3volt from the on-board regulator). Output is on P64 through the indicator LED.

Latest SVN is attached as a zip, though I have not had a chance to synthesize and test it yet.

Please note that this does not test the additional connections on the secondary JTAG bus of the FT2232. That will need updated buffer, as well as a new test application.
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Re: Bus Blaster v4 power up test success, bitstream next

Reply #21
I'm not really sure how the self-test works, but it looks like something is two bits off... here is the output I get from the self-test .bat file;

Code: [Select]
C:Documents and SettingsAdministratorDesktopbusblasterdangerous-prototypes
manufacturing_resourcesv2-selftest>BusPiratev2Test_VisualC++Express.exe -delay
-n0
Select device:
Device 0 (Serial Number: FTVDJFA1A

======================================================
SUCCESS (Connected to the FTDI.FTVDJFA1A)
SUCCESS (reset)
SUCCESS (usb parameters set)
SUCCESS (event chars disabled)
SUCCESS (timeouts set)
SUCCESS (latency set)
SUCCESS (flow control disabled)
SUCCESS (MSSPE reset)
SUCCESS (MPSSE on)
START TESTING

======================================================
        00000001        11000001
        00000010        11000010
        00000100        11000100
        00001000        11001000
        00010000        11010000
        00100000        11100000
        01000000        11000000
        10000000        11000000
        00000000        11000000
        10101010        11101010
        01010101        11010101
        00000000        11000000
        11111111        11111111
Testing complete, errors: 12

C:Documents and SettingsAdministratorDesktopbusblasterdangerous-prototypes
manufacturing_resourcesv2-selftest>pause
Press any key to continue . . .

Re: Bus Blaster v4 power up test success, bitstream next

Reply #22
Hey Skot,

Thanks for the test and update. The self test puts patterns on the FT2232's 8 ADbus pins. THe buffer loops them through the JTAG header and back to the FT2232's 8 ACbus pins. The value shown is the returned byte from the ACbus.

I am guessing the upper two bits are AC/ADbus 6 and 7

Code: [Select]
NET "FT_RTCK"        LOC =  "P49";   #AD7
NET "FT_nSRST_IN"    LOC =  "P50";  #AD6
#unused ft2232 connections
#NET "ACBUS6"      LOC =  "P40";
#NET "ACBUS7"      LOC =  "P39";

Hum - on my copy of the v4 UCF C6 and 7 are commented out. Did you fix that before synthesizing? Maybe they were randomly assigned. That could be the problem. I updated the version in SVN.

If that is not the issues, could you please run the test without the jumpers on the JTAG header, that will help determine if the problem is before or after the buffer.
Got a question? Please ask in the forum for the fastest answers.

Re: Bus Blaster v4 power up test success, bitstream next

Reply #23
Ah ha! That's prolly my fault — not sure why I commented those out. anyways, the tests pass with the following;

Code: [Select]
#unused ft2232 connections
NET "ACBUS6"      LOC =  "P37";  #AC6
NET "ACBUS7"      LOC =  "P36";  #AC7

self-test output;
Code: [Select]

C:Documents and SettingsAdministratorDesktopbusblasterdangerous-prototypes
manufacturing_resourcesv2-selftest>BusPiratev2Test_VisualC++Express.exe -delay
-n0
Select device:
Device 0 (Serial Number: FTVDJFA1A

======================================================
SUCCESS (Connected to the FTDI.FTVDJFA1A)
SUCCESS (reset)
SUCCESS (usb parameters set)
SUCCESS (event chars disabled)
SUCCESS (timeouts set)
SUCCESS (latency set)
SUCCESS (flow control disabled)
SUCCESS (MSSPE reset)
SUCCESS (MPSSE on)
START TESTING

======================================================
        00000001        00000001
        00000010        00000010
        00000100        00000100
        00001000        00001000
        00010000        00010000
        00100000        00100000
        01000000        01000000
        10000000        10000000
        00000000        00000000
        10101010        10101010
        01010101        01010101
        00000000        00000000
        11111111        11111111
Testing complete, errors: 0

C:Documents and SettingsAdministratorDesktopbusblasterdangerous-prototypes
manufacturing_resourcesv2-selftest>pause
Press any key to continue . . .

Re: Bus Blaster v4 power up test success, bitstream next

Reply #24
Yeah! Thanks for the followup. I need to build the a revision with the fixed 1.8volt rail, then I think this is ready for a small initial batch.
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Re: Bus Blaster v4 power up test success, bitstream next

Reply #25
Glad to hear it, i'll be looking forward to it!!! I'd love to bulld one

Re: Bus Blaster v4 power up test success, bitstream next

Reply #26
I've recently built the Bus Blaster v4 board shown in the photograph. It cannot be seen properly in the image, but for this build I used a Xilinx XC2C128-VQ100 instead of the XC2C64A used in the original design. Note also the ugly patch I had to perform to power the CPLD and FT2232H cores using an external 1.8v voltage regulator (as can be seen in the image, the FT2232H internal regulator cannot be accessed due to a missing pin).

I checked the board via the test program, and it successfully passed the tests (see the attached photographs). I've also succesfully used it to program a Coolrunner II CPLD board and a Lattice ISPMach128v CPLD, and I can confirm that the board is working flawlessly.

I'm sharing the compiled buffer for the XC2C128 (the svf file + the complete ISE project) just in case anyone is interested. I did not perform any modifications on the code provided by Skot for the  XC2C64A-VQ100, since it was not necessary.

Regards,

M.

Re: Bus Blaster v4 power up test success, bitstream next

Reply #27
Hi there !

I was wondering if you have any BBv4 PCB left (I have a free PCB code) ? I'd really like to build one and test it. Moreover I have access to the exact right CPLD part (XC2C64A-7VQG44C available on french Farnell with free shipping).

Thanks !

Re: Bus Blaster v4 power up test success, bitstream next

Reply #28
mikelelere - thanks for verifying the design and reporting results. I think I forgot to submit my reply last week, but I did get it onto the blog  :)

Grapsus - I will put the final v4.1 design with standard PCB footprint in the store shortly. To get it early pls email or PM me your code and address and I'll send it out today.
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Re: Bus Blaster v4 power up test success, bitstream next

Reply #29
Hi there !

@Ian I got the PCB last friday, thank you very much !

I got the components I didn't have already this morning from Farnell. I had to take the 128 cells CPLD version as the 64 one was sold out. A photo of my build is attached.

Man, this VQFP100 CPLD chip was such a pain to solder !
I didn't populate the I2C EEPROM yet, I will do it later to customize the VID/PID if everything else works fine.

My board powered up OK, the FT2232 was recognized. Then I spent two hours building urJTAG with libftd2xx. Finally the CPLD is alive :

Code: [Select]
warning: UrJTAG may damage your hardware!
Type "quit" to exit, "help" for help.

jtag> cable ft2232 interface=0
Connected to libftd2xx driver.
jtag> detect
warning: TDO seems to be stuck at 1
jtag> cable ft2232 interface=1
Connected to libftd2xx driver.
jtag> detect
IR length: 8
Chain length: 1
Device Id: 00010110110110001010000010010011 (0x16D8A093)
  Manufacturer: Xilinx (0x093)
  Unknown part! (0110110110001010) (/usr/local/share/urjtag/xilinx/PARTS)

I will try to flash the JTAGKey image tomorrow.