It looks like we removed target_present from v4. Wiring either way is probably ok, I don't think many programs rely on it.
I added your ucf to the test mode buffer folder in SVN. I made a few tiny changes:
NET "FT_DBGACK" BUFG = CLK; #AC5 is clock out in 485 mode
because FTDBGACK is clock out for a potential 60MSPS logic analyzer mode and we did make the effort to route it to a GSK pin :)
//control pins for test mode
input wire TEST_MODE_0; //has pullup, pull low to ground to enter test mode
inout wire TEST_MODE_1; //outputs high (light LED) on test mode active
wire TEST_MODE;
There are 2 new signals and pins used by the test buffer, Test_MODE_0 and TEST_MODE_1. There is a TEST_MODE_2 too, but it is unused and should be removed (I may check in one with it removed now).
#trigger pins for test mode
NET "TEST_MODE_0" LOC = "P1"; #test mode trigger pin, pull low to enter test mode
NET "TEST_MODE_0" PULLUP;
NET "TEST_MODE_1" LOC = "P64"; #test mode output pin, usually the LED
NET "TEST_MODE_1" PULLUP;
I added them to the v4 UCF and assigned the trigger pin to P1, short it to ground to enter test mode. (Make sure the on-board power jumper JP4 is closed to power the front end with 3.3volt from the on-board regulator). Output is on P64 through the indicator LED.
Latest SVN is attached as a zip, though I have not had a chance to synthesize and test it yet.
Please note that this does not test the additional connections on the secondary JTAG bus of the FT2232. That will need updated buffer, as well as a new test application.