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Topic: Open Hardware Debug/Test-logo (Read 2909 times) previous topic - next topic

Open Hardware Debug/Test-logo

Hi,
on Tokyo Make Ian was talking about the pain of testing and verification of populated PCBs.
Basically, for very high volumes, you would set-up a test card with prober-pins which fits exactly to your board.
Then you run a bunch of tests measuring voltages, currents, maybe even serial com, etc. and compare them with some specs. Either you use some dedicated test equipment or you build up your own testing circuit. Getting a test-card with prober-pins is expensive and not really practical if you only have small batch volumes.

There might be different solutions to this problem.
One could limit the position of test/debug pads/vias on a rather big raster. E.g., 0.5x0.5cm^2. Now one could assemble the required test pins into a base containing holes with the exact same raster pattern.
This would already speed up things a lot.

Another idea would be the design of a standard test-pad pattern. E.g., somewhere on the PCB you will find 4x4 1x1mm pads or vias. This gives 16 test connections to proof functionality and the same test-probe could be used over and over again for different designs. However, it would require to route signal lines to this pattern and this might have some negative influence on the signal integrity.
 
Looking at the Dangerous Prototype logo I was wondering one could even utilise the logo itself as some kind of debug/test pattern.
This would save the need to make space for another pattern and has some sort of geeky factor. E.g. telling people during troubleshooting, "please measure the voltage between the line and the dot of the exclamation mark" :) . However, this would require additional routing too.

I like the idea that open hardware includes some kind of easy and open testing/debugging features. If it could be standardized in some manner it would be even better and if it would be the logo it could be some kind of extra for DP-recognition.

Any thoughts or ideas?

Re: Open Hardware Debug/Test-logo

Reply #1 –
Nice idea, but connecting every signal path to the logo is a bad routing idea. Also you have to make the logo in pads layer then.
Still learning
-Arup

Re: Open Hardware Debug/Test-logo

Reply #2 –
Hi Arupbsk,

well it wouldn't be _every_ signal path but rather very few to test functionality. Guess most of the time, power lines are of interest as well as some dgital I/Os to check the function of the uC maybe you could add an existing JTAG or ISCP to the logo :) . I would believe these line could be safe to route on a rather small PCB. But you are right, its a trade off.
As for the pad-layer instead of the silkscreen... a golden or silver DP-logo would be nice or ?! :)

Re: Open Hardware Debug/Test-logo

Reply #3 –
Quote
utilise the logo itself as some kind of debug/test pattern.

lol :) I like it :)

You are right though. I don't worry about signal integrity at the speeds our stuff runs. I worry more about routing difficulties and of the impossibility of fitting that on many 2-layer designs.

I'm glad you brought up the test bed idea though. I keep meaning to work on that. Some sort of reconfigurable pin bead would be killer. It doesn't have to be large, just enough. Since custom made bed setups are out of the question, maybe we could constrain the test points to a bread-board compatible grid. We could make a footprint overlay to help choose placement. Then pogo pins can go in a breadboard and hit the test points.

Fortunately, most DP stuff can be tested with some form of self-test. That is always my preference because the user can also verify that hardware is work ing.
Got a question? Please ask in the forum for the fastest answers.

Re: Open Hardware Debug/Test-logo

Reply #4 –
test beds don't need to be complex, take an un populated pcb for the project you want to test, put the pogo pins on the test points(use pth test points) add a simple lexan shield.

for testing you can use a data acquisition device on all the analog, and the digital can be sent to a bus pirate.

Re: Open Hardware Debug/Test-logo

Reply #5 –
using the DP logo with some test points built in is definitely a fun idea - even though it's practicality is limited.

[quote author="ian"]Since custom made bed setups are out of the question[/quote]
if a test bed is simply a PCB, I don't see why it would need to be terribly expensive - you can get 100 test pins on ebay for ~15 USD.  So, test pins for however many test points you have, plus the cost of a PCB (or a few, depending on what the fixture looks like) - seems like even with a couple of custom PCB's from Seeed you'd be under 100 USD for a set of 10 test fixtures (plus the BOM of whatever you have connecting to them: DAQ / custom circuitry /etc).

sparkfun did a tutorial on their use of pogo pins in test fixtures a couple of years ago:
http://http://www.sparkfun.com/tutorials/138

From what some of the comments on the tutorial said, it sounds like their production has changed since this was posted - but it's still a worth-while read.
 

Re: Open Hardware Debug/Test-logo

Reply #6 –
I meant a test bed for the envisioned universal test device, like a giant breadboard with individual pin routines for each hole.

Definitely the test PCB is a quick and easy way to go. We have not had to do that for any of our stuff yet, but I'm sure some day.
Got a question? Please ask in the forum for the fastest answers.

Re: Open Hardware Debug/Test-logo

Reply #7 –
I think the labour cost are the most expensive part.
Having to do this for each and every PCB is a huge cost factor, taking that the entire PCB process is already streamed out very much the same way like printing on a paper printer.
Having someone sitting down considering how to solder the pogo pins to avoid any collision with soldered parts might together with the necessary teaching how to test the device be the real expensive part.
Using a general pattern might cut down this a lot. E.g. Eagle could have a standardized grid and use a special defined via or pad with enough declared clearance to guarantee that no component in the neighbourhood will be in the way during testing.

The other part would be .... getting some nice little hardware (buspirate and logic sniffer comes close to this) to perform the tests.
DAQ was mentioned but there are not on the cheap side.
This and a nice software which allows to easy create rules like APPLY->TEST->COMPARE.
Add this into the Eagle format allowing to define test routines already during the design in the schematics and we are much closer to what would be a complete automatic production cycle. I'm old enough to remember the good old schematics of scientific devices, which describe all possible test-pins sometimes even including a small picture how the signal should look like on an oscilloscope.  Imaging getting this functionality in your EDA software.

Re: Open Hardware Debug/Test-logo

Reply #8 –
[quote author="torwag"]The other part would be .... getting some nice little hardware (buspirate and logic sniffer comes close to this) to perform the tests.
DAQ was mentioned but there are not on the cheap side.[/quote]

The buspirate and logic sniffers cover the digital side of things, but sometimes you want to check an analog DC voltage (or possibly even a time-varying signal), this is where it's useful to have a DAQ type system - some aren't as pricey as others.  Also some have both DAC's and ADC's, which comes in really handy.  You could also build a custom DAC/ADC solution, it just requires more design time.

[quote author="ian"]I meant a test bed for the envisioned universal test device, like a giant breadboard with individual pin routines for each hole.
[/quote]
OK, I only have a vague picture in my head of what you're envisioning here.

[quote author="ian"]Definitely the test PCB is a quick and easy way to go. We have not had to do that for any of our stuff yet, but I'm sure some day.[/quote]
Yeah, I agree that self-test is the way to go when you can swing it.