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Topic: XT-IDE adapter with CPLD builds (Read 201439 times) previous topic - next topic

Re: XT-IDE adapter with CPLD builds

Reply #420 –
Fluxclene spray, made by Electrolube - works well on almost all fluxes. Spray on, leave for a minute or two, then brush (for heavy flux deposits) and spray again to rinse it off while holding the board vertically to rinse off. Then a spray with IPA (Isopropanol) but use the pure 99.7% or better stuff, such as Electrolube brand, that will help rinse off any remaining residue. They are not cheap chemicals and are more aimed at professionals, so may not suit a hobbyist.

I find acetone is too harsh on many through-hole components and can melt some plastics, but if it works for you, then fine.

Re: XT-IDE adapter with CPLD builds

Reply #421 –
Thanks for the input on that.  Interesting that Acetone can attack the plastics!

I decided to adapt my board to 100mm width and get it made by Seeed.  But, when I change a drill to anything other than 0.6mm the Seeed 1.1 DRU produces drill size errors.  So drill = 15 mils produces DRC drill size errors on layer 20, yet seemingly the same config in DPv2 BRD file passes the check just fine?  What am I missing!?  EDIT: Turned out I'd put a value in the net classes at some point.

Re: XT-IDE adapter with CPLD builds

Reply #423 –
Hi Pietja, many thanks for talking the time to put in all your test results - complete with links I see!  I can't find almost anything about your test rig (Tandon TM 7305) - what is that?

Re: XT-IDE adapter with CPLD builds

Reply #424 –
I've been thinking about BIOS and throughput, and revisited the (long) thread on vc-forum on the chuck-mod.  Chuck himself has very kindly expanded on the design changes that would be needed to speed up writes via word instructions give 80188 or V20 CPU thus,

If I were to do a CPLD version, the change that would be required would be to take into account that the write signal to the IDE interface needs to occur on the output of the high-order byte, while when reading, the read signal occurs on the input of the low-order byte. Both IN AX,DX and OUT DX,AX transfer the low-order byte first, then the high-order byte.

Is this something we could have a go at with the CPLD code? The next XT-IDE universal BIOS (V2) is being developed actively it seems so maybe there could be scope to include changes for any new logic there, or at least fork that for it anyway.

As ever, any thoughts gratefully received!

Re: XT-IDE adapter with CPLD builds

Reply #425 –
OK so I've got a circuit design for this, which adds one 74LS245 and a couple of NXOR gates to the existing v2.  Will upload a schematic once it's drawn out.  It will use 'chuck-mod' BIOS code for reads, but needs new code for writes (obviously) but also needs some changes to IDE register code, since all writes to port 300h must then be 16-bit.  No idea if it will work :)

BTW more test results have come in for the DPv2 board.  Seems like a possible issue with Western Digital drives of around 1GB, but pretty much everything else seems to work well.  There is a v2 beta of the xtide-universal BIOS just released; I'm hoping to get the non-functional drives re-tested with that BIOS soon.

Re: XT-IDE adapter with CPLD builds

Reply #426 –
As promissed here's my schematic that should provide for fast writes with the DPv2 board.  The command trigger is changed for port xx0h writes to xx1h, hence allowing the CPU to write low then high bytes, hence opening up the OUTSW instruction on the V20.  Otherwise it should work like the chuck-mod schematic.

So now I just need to learn how to use ISE :)

Re: XT-IDE adapter with CPLD builds

Reply #427 –
My compact-flash board is alive :)  Next is to work on the revised schematic.

Re: XT-IDE adapter with CPLD builds

Reply #428 –
Well done J1mbo, great to see you got it working. There appears to be a problem in the schematic you put up though. IC2 (a 74LS138) has one of it's inputs Pin 3, connected to an input on an inverter and an input on an OR gate, but not connected to any output, therefore it's simply floating.

Edit - Oops! I see you have put up another post saying that you are going to do revised schematics, so perhaps you know about this already.

Re: XT-IDE adapter with CPLD builds

Reply #429 –
I've looked at it again and realised that you have a label on it showing the node as A0, I just didn't notice it as it wasn't shown as a wire that ends with that node like I'm used to.

Re: XT-IDE adapter with CPLD builds

Reply #430 –
Hi, thanks for this!  Yes it's my bad drawing I think :)

Re: XT-IDE adapter with CPLD builds

Reply #431 –
No problem, You've put in a lot of work on this, so no problem at all.

Is it possible with this design to run two drives like normal IDE interfaces? I'm thinking perhaps it could be setup with two IDE ports and the CF slot. If it can run two ports, then presumably you could use any combination of the two ports, eg. one IDE and one CF, or two IDE?

Re: XT-IDE adapter with CPLD builds

Reply #432 –
Yes, it's possible, but not without issues.  To use CF and drive simultaneously, there would need to be PDIAG connection between them, but that's not presented by 80-wire cables at the host end.  I think it should work with a 40-wire cable though.  Also routing the signals from the CF header to the 40-pin header is tricky, would need the upper bracket hole to be moved for a start, but it is possible.

Really because of this and as 8GB CF cards cost only about £10, I thought it might be better to use both the CF and the DPv2 in a system needing both 40-pin & CF, and in that config no expensive EEPROM would be needed on the DPv2 board as the xt-ide universal BIOS can be configured to run two cards I think (with the switches on them set so the IO port ranges are different).  Actually with 32K available my board could accomodate completely seperate BIOS's for both of them anyway.

What do you think?

Re: XT-IDE adapter with CPLD builds

Reply #433 –
Nice build! Glad to see the CF version worked out so well. Your wiki is beautiful too!
Got a question? Please ask in the forum for the fastest answers.

Re: XT-IDE adapter with CPLD builds

Reply #434 –
Thanks Ian, glad you like it.

Sleepwalker - possibly I've just realised what you meant; i.e. having the card provide both a primary and a secondary IDE interface (like on a motherboard with two physical 40-pin headers), but one of them providing the CF card socket already present?  So really a 'secondary' channel supporting two drives via 40-pin.

It might be do-able if seperating IDE /CS0 and /CS1 were enough; the IDE decode logic could be extended to consider a seperate consecutive port range (say, 300-30Fh for primary, and 310-31Fh for the secondary) so the secondary controller could be hooked up to a 40-pin header.  Which way around the 'controllers' are could be configured via CPLD code I suppose.

It seems the real limitation of all the boards in this thread though is that fellow enthusiasts don't want to venture into SMT to build them.