Dangerous Prototypes Open Source Hardware

Re: XT-IDE adapter with CPLD builds

Reply #405 – February 24, 2012, 10:23:26 am

Thanks for that.

I've started a compatibility list: http://vintage-blog.peacon.co.uk/wiki/D ... lity_Notes

Pietja, would you mind posting details of your test machine and any drives tested?

Both WD drives that didn't work are ATA-2.  The Seagate drive I guess is ATA-1 (it's listed as 'AT-Bus').

Re: XT-IDE adapter with CPLD builds

Reply #406 – February 24, 2012, 10:34:14 am

Of course i will add my test data, including some CF microdrives.

Re: XT-IDE adapter with CPLD builds

Reply #407 – February 25, 2012, 12:48:12 am

Thanks, that would be great.

Can I just ask (and again, please accept my apologies for yet another noob question), but what is the purpose of the 47uF electrolytic on this board?  Value seems high compared to the stated Vin values on regulator datasheets for example.  If flash, CPLD and CF-socket all have 1uF or more close to each, I'm just wondering if the big cap is really needed at all.

Many thanks!

Re: XT-IDE adapter with CPLD builds

Reply #408 – February 25, 2012, 03:39:02 am

Hi J1mbo -

The circuit only seems to show V1a, so I assume you are talking about that. Generally when they show caps in regulator datasheets they are talking about the lowest value needed for stability. For example, if you look up something like a 7812, you would find in a typical datasheet they may recommend say a 0.2uF Tantalum on the output and a 1uF Tantalum on the input. If you read the fine print on some data sheets it will explain that this is the minimum value for stability and without it you are likely to get oscillations and instability, bigger values are quite acceptable and may assist with response. It's not uncommon with older regulators (and plenty of new ones) to have a regulator break into oscillations whilst still working (the AC oscillation riding on or modulating the DC) and they end up overheating and cooking, even though they have protection, that's why the manufacturers almost always say to put the caps very close to the regulator, that lessens any inductance in the line to the cap and so lowers the AC impedance to the return line (usually 0V) and so dampens any oscillations. This is what they mean by 'Bypassing', they are bypassing all the incoming (or outgoing) lines and coupling any AC component of the signal to 0V (or whatever you have it coupled to).

Now if you take your 7812 with a 1uF tantalum on it and put 6ft worth on wire to your power source, you end up with 6ft+6ft=12ft worth of lead, acting a bit like an inductor and a bit like an antenna also. That inductance will tend to act a bit like a spring and so the reg will have more tendency to oscillate. The leads will also pickup high frequencies to some extent and in extreme cases, this can cause oscillation, even with a small cap attached. If it's intertangled or wrapped up with other wires, it might even be acting a bit like a capacitor coupling parallel signals into the wires to the reg or the reg output, back to the reg input (i.e. an oscillator).  The input cap dampens those oscillations by providing a low impedance to AC signals, but if the cap is too small and the tendency for oscillations too big, then it might not be enough. The load pulling more current can also cause this (it changes the current on the input of the regulator too don't forget), so it is generally better to have a bigger cap on the input than the output (there are other reasons for this too).

If you are feeding from a relatively clean supply in close proximity, you can get away with lower values, but bigger won't hurt and can help, up to a point. 2000uF might be a bit big if you were feeding the reg from a switchmode supply for instance, but might be fine if coming from a rectified AC supply of suitable capacity.  Values of 47uF are not unusual at all and really it's not a terribly big value at all, in fact I would commonly use 100uF or more in circuits such as this.

Now consider the cap on the Output of the reg, this too generally has a minimum value required for stability, but can be increased to swamp any oscillations. The bigger the load and the longer the lines, the more chance it has of oscillating; likewise if it's switching loads faster.  By installing the cap close to the reg, you tend to dampen those oscillations and you will also dramatically improve the instantaneous response so that fast switching loads don't cause nasty spikes momentarily.  The cap can range from small to a couple of orders of magnitude bigger, depending on the reg, the load, etc.

Why have two different value caps on the output?  Well Electro caps are good at low frequencies, but not so crash-hot at high frequency (partly because of their construction), small ceramic caps tend to be great at relatively high frequencies (or fast switching speeds), but their low values and construction means they aren't so good at low frequencies. By having a small value you will get better response to the higher frequencies / higher switching speeds, but less overall capacity, with the bigger one (usually by at least an order of magnitude) in parallel, you provide a good reservoir for the lower frequency loads and cover just about all the bases.

In the real world the loads will be hugely mixed, even for the same project; different construction methods, different wiring, different brands of load (eg. different brand chips, different brand CF cards) and so it's extremely hard to predict exactly how the circuit might behave AC wise.  If you have a bigger load and longer lines on the output, the same sort of thing applies. If you switch a largish load suddenly and it's a distance from the reg, the inductance of the leads and the speed of the reg, will mean it will take a bit long to react and it will take longer for the extra capacity to reach the device also. This can cause the voltage (and current for that matter) to dip for a split second at the load and this can cause all sorts of odd and unexpected results. By putting additional bypass caps near the load, you effectively give the line a storage reservoir right at the load, ready to supply that extra bit of grunt when needed.

That extra capacity also slows the rate of change on the line (di/dt and dv/dt) and so the effects of the line inductance are lessened and the load on the cap back at the regulator output is also lessened. The net effect of all of this is better regulation at all practical speeds and much more stability in most cases - to the point that most hobbyists and plenty of digital engineers have no clue that any of this AC stuff and things on the verge of instability, is actually going on in their circuit.

If it were my circuit, I'd be running something bigger near the CF card, say a 10uF tant in parallel with a 0.1uf or 0.01uF ceramic, but then the lowish value reg might not like that. The 47uF on the input is fine and could even go bigger with no problems.

This is only scratching the surface with a teensy bit of rough AC theory plonked in, but gives you an idea.  Hopefully I haven't tied you up in knots and confused the heck out of you and forgive me for hijacking this thread, but you asked the question! AC theory can get pretty involved, especially when you're taking frequencies that 20 or 30 years ago were only for RF engineers, the higher the frequency, the more weird it gets - like two open circuit 1/4 wave wires acting like a short!

Re: XT-IDE adapter with CPLD builds

Reply #409 – February 25, 2012, 11:57:13 am

Hi Sleepwalker3, thank you very much indeed for posting this superb reply!

Re: XT-IDE adapter with CPLD builds

Reply #410 – February 25, 2012, 01:28:12 pm

Thanks for the compliments, glad you liked it.

Re: XT-IDE adapter with CPLD builds

Reply #411 – February 27, 2012, 09:22:57 am

Hi Sleepwalker et al, about these caps.  Is there a downside to 1uF X5R 0603s throughout (or even larger, 2.2uF maybe), instead of the 0.1uF on the power pins?  I'm just thinking that because these tend to be sold with 50 min quantity so it could reduce waste when assembling the board if they were all the same.

Many thanks!

Re: XT-IDE adapter with CPLD builds

Reply #412 – February 27, 2012, 01:50:58 pm

0.1uF is best for the small spikes we are trying to filter. Actually I read an appnote a while back that said modern logic (eg CPLDs) do best with 0.01uF or both. I would not go higher for decoupling caps.

Re: XT-IDE adapter with CPLD builds

Reply #413 – February 27, 2012, 02:03:45 pm

Thanks Ian, I've found that too now.  TBH it's all a bit over my head so I'll stick with 0.1 :)  I did find the switching speed and output impedence though (here).

Re: XT-IDE adapter with CPLD builds

Reply #414 – February 27, 2012, 04:04:36 pm

J1mbo, Ian was correct, you don't want to replace the 0.1uF with 1uF, but you can use both close together. Re. Ian's comment about the .01uF, actually the recommendation these days is to actually vary the caps in value at various points around the board, typically by an order of magnitude. This mainly applies to the smaller caps, as it will have much less effect on the bigger values.

The idea, In short, you would stick with the typical 0.1uF distributed around the board at each chip or device and every here and there you would fit a .01uF  - The reasoning behind this is more for large production boards where the layout can often be a lot of duplicated sections or long repeated rail sections at regular intervals. A long section of track with regular lengths to each cap and a particular signal generated, can, in certain circumstances act like a specifically tuned filter with the track being an inductor reacting at a resonant frequency and allowing a very narrow band of oscillation through.

This sort of thing is a bit '1 in a million' type thing and is more of concern if you were designing some piece of hi-end military hardware that needs to behave under extreme circumstances or a car computer that had to withstand stringent testing and extremes of electrical noise. For the most part, for hobby stuff like this, you're not building a space shuttle, so if you stick with a general rule of thumb of at least 1 x 0.1uF for every chip / device (more if the manufacturer calls for it - eg. micros often need 4 or 5 or more at distributed locations) and at least 1 x larger low ESR electro or Tant (pref) for every 5 or so chips then you should be fine.  The values really aren't critical, if you had just .047uF instead, it would make no real difference to 99.9% of circuits. If in doubt, add another one!

Re: XT-IDE adapter with CPLD builds

Reply #415 – February 28, 2012, 01:15:58 pm

Many thanks for the extra explanation on this - very much appreciated.

Re: XT-IDE adapter with CPLD builds

Reply #416 – February 29, 2012, 12:34:28 pm

Hi, I was wondering what you experts use to clean boards up after assembly.  I've been using isopropynol bath and tooth-brush but can't quite reach some residue under the SMD pins etc.  Many thanks!

Re: XT-IDE adapter with CPLD builds

Reply #417 – February 29, 2012, 03:51:15 pm

If the flux is water soluble, a dishwasher.  But as most aren't, I use flux remover and a toothbrush followed by alcohol and a toothbrush.  I can never can cleanup 100% of the flux under a chip either, but cleaning flux residue isn't necessary in general.

Re: XT-IDE adapter with CPLD builds

Reply #418 – February 29, 2012, 10:54:26 pm

Thanks Alan.

In case anyone is interested, I just assembled a V1B board, which works just fine.  The only change I made to it was to tie CSEL (pin 28) to pin 30 (ground) on the underside of the header instead.

Re: XT-IDE adapter with CPLD builds

Reply #419 – March 01, 2012, 04:37:25 pm

I use nail polish remove, perfumed when available, and a toothbrush to clean flux for photoshoots. Wear safety glasses, flying bits of acetone (or similar) is not great.