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Topic: Logic Shrimp variation (Read 13546 times) previous topic - next topic

Re: Logic Shrimp variation

Reply #15
Probably, you can get complex with it, but eventually you'll lose a little bit unless everything accounts for the exact number of cycles to change between timers (hard to do with interrupts running).

A parallel ROM or RAM chip could be used, that's the model the bitscope uses.
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Re: Logic Shrimp variation

Reply #16
the datasheet on the pic says theat the timer1 gate can be driven trough the timer0 overflow, and this is all done trough hardwer, not trough inerupt, am i missing somethin
best regards FIlip.

Re: Logic Shrimp variation

Reply #17
Could be, I didn't read that far into it.
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Re: Logic Shrimp variation

Reply #18
timers would work but flash would not (limited number of write cycles as Ian mentioned).

as for the parallel ram chips I am using some parallel ram with mcu + oscillator + counter to get the 8 channels on some old project of mine but the problem I have is that triggering sucks as I miss few samples always and I don't have the ring implemented so I always start from address 0 and fill the ram to the end. I had a plan to put a cpld on the board to make it better (to do the triggering from cpld and not from pic, and to have counter on cpld and not to use external counter) but then first OBLS came to my life that got the "lot of channels + good triggering" already done and now LogicShrimp came with 256k samples ... no I just don't see a value of losing time making it again :D .... I'm still thinking of making something between logic8 and logic16 with 2232H + some buffer on board as I get almost full usb transfer there when I use linux .. but that will really need to wait some better times...

Re: Logic Shrimp variation

Reply #19
I have a similar idea, but for a dso, RAM+CPLD+FT2232+pic24+ADC
FT chip chanla A 245 sync would be conected to the cpld, Chanel B SPI would be conected to the pic, and the cpld would be conected to all, the cpld would do everything, the pic would set up the  trigering, data flow and start/stop, depending on the instructions from the FT2322. so basicly the PC would controll all.

-sorry for going offtopic
best regards FIlip.

Re: Logic Shrimp variation

Reply #20
not really a viable solution for dso because you need to have triggering done on the board. triggering on the pc is way too slow. When you do triggering on the board then you only need to send "one screen of data in 1/30sec" to the pc and for that even BT is enough. It is much more important to have a good triggering system on the board and for that when dso is what you make cpld don't have nearly enough power and you have to go fpga... best you could do with cpld is something like http://www.ulrichradig.de/home/index.php/avr/avr-dso

Re: Logic Shrimp variation

Reply #21
You probably only need FT2232 or PIC24. I made a simple LA in verilog that drives SRAM and fits in a small 72macrocell CPLD. There are even pretty illustrations :) That might help you get started:
http://dangerousprototypes.com/docs/Lul ... c_analyzer
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Re: Logic Shrimp variation

Reply #22
//end of off topic
Thanks ian, that helps alot, i expecialy like that you added how much of the CPLD is used up, excelent work. Id probably use one of those cheap spartan FPGA for more headroom and speed.
best regards FIlip.