Digital Sampling Oscilloscope attachment (DSO wing)

[ian]

This is a new topic to discuss a digital sampling oscilloscope 'wing' that will attach to the extra 16bit header on the SUMP PUMP.

Our general goal is a small expansion board with a 50MHz+ parallel ADC and compatible analog front-end.

Some steps we need to take are:
1. Choose a parallel ADC chip
2. Design the analog front-end circuit
3. Create a prototype expansion board (or wing)
4. Modify the SUMP FPGA design and SUMP software to display DSO output (may already be in the SVN version)

All contributions and comments are welcome. Our progress will be updated here, and you can also browse the SVN for this project:
http://www.gadgetfactory.net/gf/project/dsowing/

[Entropy]

The Analog AD9288 is quite popular with oscilloscope manufacturers - the Rigol DS1000E series use them.  (The 1052E and 1102E use 5 AD9288s in parallel with phase-shifted clocks.)

However, with a 16-bit wing, you'll be able to at best achieve 200 MSPS on a single channel with the -100 parts.

Unfortunately, since the current "sump pump" design has the voltage buffer for the other 16 channels permanently installed, you may not be able to use that 16-bit path for another ADC.  Two AD9288s would get you to 400 MSPS.

[LeissKG]

This is a new topic to discuss a digital sampling oscilloscope 'wing' that will attach to the extra 16bit header on the SUMP PUMP.

Even if it is a wing, would you consider rotating the connector 180 degrees. This may make the pcb stack more compact. You may
obscure some connectors on the sump pump pcb but I think they are either normally not needed during measurement or useful on
the extension board like clock and trigger. This way you could build a cross trigger feature ( scope triggers LA or vice versa ).

Some relevant information for an Input stage can be found at

http://www.ssalewski.de/DSO.html.en
and
http://www.ssalewski.de/DAD.html.en

Another question is do you really mean 50MHz and not 50MSPS? I think for a 50MHz design you need between 250 to 500 MSPS. For that sample
rate you don have enough pins on the connector. Most fast A/D subsystem that I know of have either an fast A/D with an on chip demux or like the
Rigol scope a group of slower A/D that have phase shifted sample clocks.
 
National has also fast A/D, have a look at
http://www.national.com/analog/adc/evalboard_high_speed_adc

Klaus Leiss
 

[LukeS]

What bit resolution and number of channels where you thinking for the DAC.  Also where is the data form the DAC going to be stored? A one channel 8-bit DAC at 50MSPS (enough to capture a 5Mhz signal with okay resolution) will fill up the 6Kbits of FPGA RAM in 1.5ms (750us with a 16-bit DAC) and that is with no logic channels being recorded.

[LeissKG]

Lets try for a more precise requirements list.

 100 MSPS A/D converter  ( I am not sure that sample rate is achievable without problems )
  20MHz Analog frontend  ( This is to high for the sample rate above, but you can at least check if the usual microcontroller oscillators swing).
  1 to 20V input stage         ( in 5 or more steps )

As Luke mentioned the buffer depth is not great but I can remember fancy Tektronix scopes with less buffer memory. I also think in Luke's
calculation is off. I get 120us at 50MSPS until the buffer is full.
 
Klaus Leiss

[jack.gassett]

Here are some similar projects that we can gather information from:

http://www.fpga4fun.com/digitalscope.html
http://mhz100q.sourceforge.net/
http://yyao.ca/projects/oscilloscope/
http://www.bitscope.com/design/hardware/
http://www.bitscope.com/design/hardware/analog/

Here are some potential chips:
Texas Instruments
THS1040IDWG4 (and THS1041DWG4) - 40MSPS, 10bits, 3v3, 28SOIC, $6.40 ($6.80)
THS1031IDWG4 - 30MSPS, 10bits, 3v3, 28soic,
ADS8411IBPFBT (and ADS8412IPFBT) - 2MSPS, 16bits, 48TQFP
ADS831 - 80MSPS, 8bits, 5V (3v3 interface), SSOP20, $3.95

DS/Maxim
MAX1198(1197) - 100MSPS (60MSPS), 3V3, 48TQFP, $10.50 ($5.80)
MAX1449 (/8/6) - 105MSPS (/80/60MSPS), 10bits, 3v3, 32TQFP, $10.70 (/$8.35/$6.25)

National
National Semiconductor ADC08060/08100/08200

Analog Devices
AD9283

[jack.gassett]

For the first revision I'd like to propose these specifications/scope (Which are very similar to what LeissKG has proposed).

-100 MSPS 8 bit A/D converter.
-20-50 Mhz for the frequency that can be effectively sampled. The general rule of thumb I've seen used is to use the Nyquist Frequency to determine this. If we use a 100MSPS A/D converter then the Nyquist Frequency should be 50Mhz. This is assuming an ideal filter though so in practice we will probably not achieve this.
-Op Amp to allow sampling of 1V - 10V. I'm not sure if we want to have multiple stages in the first revision. If we do want multiple stages how would we want to go about it? With a DAC or a physical means of selecting multiple voltages?
-Filter that sets a high impedance of 1M ohm which matches the impedance of most Oscope probes. Other options are 50 or 75 ohm impedance.

Optional
-Removable Anti-Aliasing filter like used in the 100MHZ project. The downside of these filters is that they are 50 ohm impedance.

Jack

[jack.gassett]

Samples

The Sump Pump Java client has an option to represent sequential channels as an analog signal. So I think the worst case scenario is that we will offer a bitstream that configures all of the available BRAM 8 bits wide, this would give us 24K samples.

The hope is that a future version of the Sump Pump design will integrate SDRAM.

Jack.

[LukeS]

-20-50 Mhz for the frequency that can be effectively sampled. The general rule of thumb I've seen used is to use the Nyquist Frequency to determine this. If we use a 100MSPS A/D converter then the Nyquist Frequency should be 50Mhz. This is assuming an ideal filter though so in practice we will probably not achieve this.

I though the double nyquist rule of thumb really only applies to frequency counting without aliasing.  From what I understand you can not accurately represent a signal at half nyquist frequency unless it is a perfect sign wave.  With 100MSPS you would only have two data points per a 50Mhz signal's period.  So you would not be able to see any noise or transients on the signal.  Let me know if I am wrong I like to learn something new.  Either way it will still be useful for monitoring >20Mhz signals accurately.

[IPenguin]

To add to the confusion regarding DSOs -- > Agilent application note defining oscilloscope bandwidth

With 100 MSPS a bandwidth of 10MHz to 15MHz can be achieved depending on the filter used.

Here is an other DSO design - Web Based Ethernet Oscilloscope - including schematics and many more details. The analogue input and the A/D part are within the range defined by Ian and Jack.

[jack.gassett]

LukeS,

Thanks for the info, I don't have much practical experience with this topic so I am simply re-stating the rule used in other projects. It's good to get input on the validity of that rule.

So it sounds like we should expect 20Mhz with a 100MSPS A/D chip for non-sinusoidal signals?

Thanks,
Jack

[rcaetano]

this project seems another great ideia.

but why would we aim for such high signals? why not lower the costs or maybe trnafer the costs to more hardware that could provide more functionalities even thought with lower bandwidth?

why not a spectrum analyzer (hardware assisted)?

(newbie here, sorry for the post)

LukeS,

Thanks for the info, I don't have much practical experience with this topic so I am simply re-stating the rule used in other projects. It's good to get input on the validity of that rule.

So it sounds like we should expect 20Mhz with a 100MSPS A/D chip for non-sinusoidal signals?

Thanks,
Jack

[LukeS]

Jack,
I am much more of a digital person then analog but most scopes on the market have a 10x plus sample rate over there rated frequency.  So we can probably safely say it can do 10Mhz and maybe up to 20Mhz sloppily.  I think most people will be using it for signals under 10Mhz.  When the next version of the logic analyzer comes around that has SRAM and all the bugs are worked out of the current setup another higher sampler rate wing could be something really cool.  I am pretty excited about this whole project.

[LeissKG]

this project seems another great ideia.

I concur it is a great idea.

but why would we aim for such high signals? why not lower the costs or maybe trnafer the costs to more hardware that could provide more functionalities even thought with lower bandwidth?

I don't think this are high signals. A 10 to 20 MHz scope is at the lower end of usefulness. And the parts are not that expensive. You can get an
200 MSPS ADC ( e.g. ADC08200CIMT) for around $10.

why not a spectrum analyser (hardware assisted)?

A lot of the spectrum analyser functionality is basically a scope plus software. But this would normally require a deeper buffer.

[Gridstop]

It would be pretty nice/easy to do differential measurements in hardware so you don't have to store both samples, yes?


And off the top of my head crazyness...

This is probably a ridiculous idea, but all this talk of high speed ADC makes me think if a v2 of SUMP ever shows up, it might be a worthwhile target to try to implement basically half of the gnu universal software radio. (Cypress EZ-USB High speed, FPGA, single AD9862 [or just a 12bit ADC-only rather than codec, and could be on a header rather than installed, as with a DSO ADC/frontend], and USRP-compatible header for the peripherals.) It would be interesting to see at least how close you could get for rather less than the $700 the USRP costs.

My guess is you could make a single board that could do buffered logic analysis as well as optional DSO/software radio receiver upgrades for a fraction of the cost. But maybe the market is too limited for that. :)