Sample lenght

[robberknight]

Hi,

I was looking for a DIY logic analyzer and found your project. Looks very interesting!

I haven't done anything with FPGAs yet, so forgive me a dumb question: I guess that you plan to use internal BRAM to store the samples within the FPGA. The XC3S250E has 216KBit / 27KByte of BRAM. Is that correct? That doesn't seem much to me.

Wouldn't it be possible to extend the storage with something like this:
http://www.micron.com/products/partdetail?part=MT45W8MW16BGX-701 IT?
To me it looks like you can drive it in continuous burst mode with up to 133MHz and then store a word with each clocktick.

Or do you not have enough free pins left to add RAM like that? Or do you not want to add BGA components or fear the additional cost of the RAM?

Kind regards,

R.

[jack.gassett]

The PSRAM is a very interesting option, I even made an attempt in the past to integrate it. The biggest obstacle I ran into is not so much the BGA package but the pitch of the pins. The pins are so close together that it became unpractical to break out the required signals with a double layer board. If we ever make this a 4 layer board then maybe we can use the PSRAM chip.

But most likely we will be best off with a SDRAM chip in an easier to use package in a future revision.

[robberknight]

Hi Jack,

thanks a lot for your quick reply.

You are right, I haven't thought about the need to route the pins away from a BGA...

And how about "classical" SRAM, available in regular TSOP, e.g.
http://www.issi.com/pdf/61-64LV51216.pdf? The 10 ns version seems to be about 12 $ at digikey. It is only 8MBit / 1 MByte - but I think even that makes a huge difference in usability of the analyzer.

Kind regards,

R.

[jack.gassett]

I'm leaning towards SDRAM because you can get 32MBit chips for a few dollars. Looking at my notes, an 8 bit SDRAM part requires 30 pins on the FPGA which would only leave 21 bidirectional pins with the FPGA chip we are using now. So we will probably need to move to a chip with more available I/O pins to make it work.

Our intention is to add memory in a future revision, for now we want to get it into a working product with the 6K of BRAM that we can squeeze out of the S3E-250 chip.