PCB design

[RichF]

Per:
http://www.xilinx.com/support/documentation/application_notes/xapp453.
says resisters are need to couple 3.3v signals to the dedivated pins of the FPGA  "jtag. Prog  etc"  when Vccaux is 2.5v 

I didn't see them in the current design

[ian]

I took a look through xapp453. We aren't using an 3v3 on the JTAG pins. Done and PROG_B are held to 2v5 with a pullup (open collector config), so the pic will only pull them low. INT_B is held to 3v3 with a pullup as specified in the other programming datasheet.

The only thing I'm not sure about is the ROM chip connections. The ROM chip is at 3v3, but I believe that's OK on all four interface pins.

I'm still learning about the FPGA setup though, so I could certainly have missed something.

[jack.gassett]

We should be ok with the FPGA header. The JTAG pins are always at 2.5V, even if VCCO is set to 3.3V the JTAG pins still operate at 2.5V. The 3.3V app note is if you are going to use a 3.3V JTAG programmer (Such as a 3.3V ft2232). In our case we have put 2.5V on the VREF pin, which is the pin that will provide power to any attached JTAG programmer. So any attached JTAG programmer will operate at 2.5V as well instead of 3.3V.

The SPI pins are dependent on the VCCO settings which we have connected to 3.3V. So all SPI communications should happen at 3.3V.

This is my understanding of how both systems should work, it is great to have other people take a look to see if they agree.

Jack.

[ian]

The PCBs finally arrived. They left the factory on 12/28, then sat in sorting (according to tracking) until 1/14 and arrived on 1/20. The actual shipping wasn't bad, just the processing.

I haven't assembled one, but I'm about to start.

There's a minor issue with the USB jack we chose, the retaining bump placement is non-standard. It's fine if you cut/sand then off (I used finger nail clippers). I tested with one of the USB jacks I usually use, and it fits, but the shield connector doesn't align with the footprint. This isn't usually a problem, but some idiot put a power via between the pads where the shield would land on it (that was me). Thankfully, this is easy to correct in the final revision (and/or we use a correct jack).

[ian]

Here's a picture of the parts.

[ian]

One board done, one to go. The first one took about 90 minutes, including e-mail breaks. I had to reseat the buffer chip about 3 times, it was a real pain.

[ian]

Argh! I built the board in stages and tested after adding each major chip. It was all good until I added the FPGA at the end. Short.

I inspected with my loupe like crazy and couldn't find anything. Then I noticed that the FPGA has two dots, the larger one and the smaller one next to the folded edge. The folded edge is obviously the 'correct' dot, but I just looked for the dot and not the edge. You can see clearly in the photo that I put the FPGA in backwards. I removed it and put in a different chip correctly, now it powers up fine. Unfortunately I imagine I killed one first FPGA.

[jack.gassett]

Ian,

I did the same exact thing with the first board I built that uses the Spartan 3E chip, but it took me a lot longer to realize my mistake. If memory serves me correctly, it was a couple years ago, the chip was fine once it was oriented correctly.

Jack.

[jack.gassett]

Ian,

As far as the buffer chip goes do you think we need to adjust the footprint to make it easier to solder? I used a script from the cadsoft website to generate the tsop footprint. Do the pads need to be lengthened?

Jack.

[ian]

I thought it's just a lot of tiny pins to get lined up, I didn't think anything could be done.

[Scorpia]

nice looking board in the end.

but damm that pic looks big. is it worth looking into a smaller footprint for the pic on a later revision?

might free up some board space or reduce the pcb size a little.

either way, looks nice guys.

[ian]

The 18f2550 usb pic has an integrated 3v3 regulator and only comes in SOIC. I thought the 24j50 was the same, but it turns out there's an SSOP version. I'd have no problem using it in the future, but we still need the board space for the other components.

[jack.gassett]

Here's another picture of a built prototype board:

[IPenguin]

I received a prototype assembled by Ian yesterday - close to pick and place quality - thank you very much :)



Ian, if you need an extra FPGA or any of the other components, let me know. I have some spares and can ship them to you.

[jack.gassett]

Better quality picture of prototype board.