PCB design

[IPenguin]

@RichF: the 10cm x 10cm limitation does not only pertain to Seeed's fusion service but to the free version of Eagle CAD as well ... maybe Ian and Jack considered this as well.

[jack.gassett]

Checked in new revision with following changes:

-Routed OE and DIR pins on buffer.
-Connected Wing ground pins to ground.
-Added two number sets to the LA headers.

I think at this point is just needs a thorough checking and then it will be ready.

[jack.gassett]

Rich, I looked at routing the control pins to the FPGA but wasn't able to do it without seriously disrupting the ground plane.

Jack.

[IPenguin]

The design looks like it's getting very very close to be sent to the PCB manufacturer for prototypes soon! :)

Updated the block diagram to the latest PCB design release

[ian]

A quick note on the license:

Jack and I discussed it a while back, and I documented the change in the change log. I don't speak for Jack, but I had two motivations for the license change.

First, I copied parts from some of my previous CCTs that included SparkFun library parts. The (old) SparkFun library was NC, so until those parts are out of the design it has to be NC to comply with the SparkFun license.

Second, because I do the preorder thing with Seeed there's a delay in the hardware being available. It's embarrassing when my new projects are ready for delivery on eBay before I can deliver my first unit (last 2 Bus Pirate designs, for example), and I feel like that's unfair to the people who support my work through hardware purchases.

My current inclination for my personal projects (not necessarily this design because it's a partnership) is to initially release them as CC-BY-SA-NC, then toss them in the public domain after the initial preorder is delivered. For my projects, I'm really only concerned about the final PCB art, I don't usually place limitations on the schematic or firmware, for example.

[ladyada]

A quick note on the license:

Jack and I discussed it a while back, and I documented the change in the change log. I don't speak for Jack, but I had two motivations for the license change.

First, I copied parts from some of my previous CCTs that included SparkFun library parts. The (old) SparkFun library was NC, so until those parts are out of the design it has to be NC to comply with the SparkFun license.

Second, because I do the preorder thing with Seeed there's a delay in the hardware being available. It's embarrassing when my new projects are ready for delivery on eBay before I can deliver my first unit (last 2 Bus Pirate designs, for example), and I feel like that's unfair to the people who support my work through hardware purchases.

My current inclination for my personal projects (not necessarily this design because it's a partnership) is to initially release them as CC-BY-SA-NC, then toss them in the public domain after the initial preorder is delivered. For my projects, I'm really only concerned about the final PCB art, I don't usually place limitations on the schematic or firmware, for example.

completely understand - i'll assume the current license is the 'final one' - but if you & jack decide otherwise please post up your decision :)

also, where is this mysterious changelog? all ive seen are attachments. is there a git repository i didnt see?

[ian]

I'm sorry, I thought I linked to the post:
http://whereisian.com/forum/index.php?topic=156.msg1145#msg1145

It's not so much a change log, as a log of our changes :) I posted a copy of what I wrote in the SVN commit notes to the 'rough design' topic. The project files are hosted in Jack's SVN at the Gadget Factory, and it should have a record of our daily commits.

[ian]

Here's another update. I didn't post a log for the last one, so this is actually my previous two commits change log:

*Reordered PIC->FPGA connection to get rid of via/jumper.
*Reordered buffer->FPGA connection for shorter, straighter connections.
*Changed a few caps to 0603
*Moved PROG_B resistor to a better spot.
*Made a mess of LED and PROG_B routing, but will fix later.
*DRC is OK for all FPGA->buffer connections.

part II:
*Swapped PIC->ROM connections for cleaner routing.
*Cleaned up LED and PROG_B traces, I think it's much nicer now.
*Moved JTAG TDI so it doesn't cross as many I/O traces.
*cleared all possible DRC errors at 8mils.
*Moved top input traces down, made shorter, straighter.
*Where parts still had numbers: moved for readable placement (mostly PIC side).
*Added DP logo

Still to do:
*Add Gadget Factory logo
*I still think the PIC->ROM connection could be cleaner
*Verify 20mhz crystal footprint/package
*Improve ground plain
*Value/part number labels???

[LukeS]

I could be missing it but I do not see the CLK and Trigger out headers in the schematic that are in the block diagram.  There is a trigger out pin that is connect to a LED but no pin header.

[ian]

Changes:

Jack made these changes:
-Fixed all traces with funny angles.
-Verified all nets on transceiver, s3e, and SPI Flash.
-Created ucf file and synthesized with VDHL design to verify placement of pins.

I made these:
*Changed crystal to cheap HC49 package
*Removed 0.01uF cap from Vusb
*Changed Vusb cap to 0603
*Rerouted MCLR for better ground plain
*Cleaned up around ROM to fit HC49 crystal
*Reoriented LEDs so traces are away from crystal
*Changed 10uF tantalum VREG output caps to 1uF 0805
*Added extra ground jumper under Q2 to PIC side
*Renumbered a few parts so like values are together
*Changes pass Fusion DRC (added DRC to SVN)
*Fixed labels on parts I disturbed.

After we sleep on this, it might be ready to go!

[LeissKG]

I don't know how often I looked at this, but it did never register that there are no mounting holes for the board. Do you have a matching case that does not need them? If used without a case at least some holes for a stand-off would be nice. Any metallic residue on the work surface might kill it otherwise.   

[ian]

You're right. We should size it for an available case when the design is complete, and add mounting holes.

[IPenguin]

Good point, mounting holes would be much nicer than glueing rubber feet under the board ...

For the Clk_Out and Trigger_Out signals it's correct that those signals are not brought out to a header.
Unless Jack will go through the effort of routing them to the wing header they will have to be implemented in VHDL by using I/O signals on the wing header when needed ...
I will wait for Ian's and Jack's final say before updating the block diagram.

[jack.gassett]

How important are the Clk_Out and Trigger_Out signals? What are the usage scenarios?

Here are some possible solutions to add them:

-Assign Clk_Out and Trigger_Out to the Clk_in and Trigger_in headers in the ucf files. This may not work with some of the usage scenarios people may have had in mind.

-Assign Clk_out and trigger_out to the RHCLK lines on the Wing header. We will only be using one DCM so it should be able to be placed in the correct quadrant to drive the RHCLK lines. I've never done this before so there is always the possiblility that it will not work like I think it works in which case we will not be able to drive clk_out since it is not connected to a global clock line.

-If we assume that we can place the DCM in the correct quadrant to have clk_out on a RHCLK or LHCLK line then we could use one of the LHClk lines on the top for a clk_out header and have the trigger_out LED also connected to a header.

-If we want to place clk_out on a global clock line then we would have to sacrifice one of the fpga_aux lines going to the PIC. I don't think we want to do this.

I want to gauge how important this is because placing a header, especially a global clock header will require some rework and possibly some compromises.

Jack.

[jack.gassett]

Ok, I just looked at the board design and how about this?

What if we add two more pins to the clock in and trigger in header and then we route fpga_aux3 which is connected to a global clock to clock_out. Then we connect fgpa_aux2 to trigger out. So fpga_aux2 and fpga_aux3 can either be used as a connection to the PIC or as clock and trigger outputs.

We would then use fpga_aux0 and fpga_aux1 for the rx and tx lines from the fpga to the Pic.

Jack.