PCB design

[ian]

This is a new thread to continue the SUMP hardware development.

[ian]

Also posted in the new thread...

PIC side is tentatively routed, files checked into SVN. Will do DRC and cleanup tomorrow.

Changed:
*Routed PIC power.
*Moved MCLR resistor.
*Moved, cleaned up power supply.
*Added 5volt supply pin to UART connection
*Added ground VIAs to all ground pins.
*Moved a few traces here and there for cleaner routing.

Need to do:
*Connect buffer control pins, power.
*Route FPGA DONE pullup
*Choose pins for FPGA ARMED/TRIGGER LEDs

[jack.gassett]

I checked in a new revision with the following important addition that I wanted to get some opinions on:

I added a ground pin on each side of the Wings connectors IO lines. This makes the Wing footprint the same as the buffered connector. So any leads that we can come up with should work with the buffered connector and the Wing connector.

[ian]

Is the VIA in the middle of the FPGA power pad needed? I think I might have dropped that by accident.

I like the extra ground pad.

[jack.gassett]

It looks like that via can go away. I removed it and and added to SVN.

Other changes checked into SVN:

-HSWAP connected to ground. This is how I have it with the design I tested SPI Flash with.
-Power partially routed for the buffer.
-Header added to the top of circuit board.

[jack.gassett]

New version is checked into SVN.

-Everything is routed.
-Passes DRC.
-Added new header with Ext_Clock_In and Ext_Trigger_In

Ian, I had to add a new header for Ext_Clock and Ext_Trigger and it required moving some connections to the microcontroller around. Can you take a look and make sure everything still looks good on that side? I'm not too happy abou the location of this header but the Ext_Clock input needs to be on a Global Clock which limits us.

We can make branch of this board with two buffers, since it will change the size of the board I want to hear from Ian before proceeding.

TODO
-Make corrections to the anchor point on the Wing footprint.
-Make sure constraints are correct for SeedStudio.
-Much more verification.

[RichF]

I posted this to the old tread by mistake   

Attached are the zip files for the 16 bit buffer  option I proposed.
note the following changes
    I moved the termination resistors to minimize the added board length.
    I slid inputs 1-9 down a pin on the FPGA to accomodate the direction control pin  routing
    The input0-7 order has been reversed on the connections to the FPGA
    inputs 8-15  have been attached to the FPGA's pins  2-5 & 9-12  The direction control for port b was attached to FPGA pin 15.  I wasn't sure if pin 13 (IP) could be used?  Was it okay to use these pins for the second port?
 
I am not a FPGA expert so let me know if I screwed up the FPGA connections 

The board is 4.4in long verses the original 3.65in  but  with a little effor it can be reduced  Also we could use the SOP package which is  .1in narrower

[RichF]

re IPenguin  remarks on the old thread:
   Let me reiterate the main idea is to add a little extra board space for depopulated options (<$.50).    The base board would not include the 2nd tranceiver or termination resistors.  The Resistor pads would be initially bridged.   All the user would need to do, would be to use an Xacto to cut the bridges  and add resistors of his/her choise.
As to 1x18 etc or 2x9 configuration, with the 2x9 configuraton  the user would purchase either 1 or2 probe cables  since they would be identical.  This keeps the base offering at a cheaper 8 probe cable.
Ideally an addon kit would be availabe having the 2nd probe set and transceiver  and maybe a few termination resistors.   The same 2x9 header could be used on a future "wing" to provide 24 or 32 channels

[Scorpia]

i have been keeping an eye on this cause i think its a great idea.

I have a question thats been bugging me

Why the funny layout for the addon board connecctor? wouldnt a 2x 24 (or what ever size) be cheaper and easier to work with?

anyway im sure you have a reason but just seems strange to me. Also i would suggest aligning the headers across the top of the board. just look better.

[ladyada]

hey just noticed the license on the board is CC BY/SA/NC...since im pretty gungho about completely open source hardware im going to bow out of following this project - but please keep me updated when its in RC state, as its very very cool and i'll post about it on adafruit :)

[jack.gassett]

Checked in design using a 16 Bit Transceiver with 4.5ns speed rating.

http://www.onsemi.com/pub_link/Collateral/MC74LCX16245-D.PDF

[jack.gassett]

I have a question about peoples opinions about numbering. The Sump Java client starts numbering with Channel 0. Do people prefer starting with Channel 0 or Channel 1?

Jack.

[IPenguin]

@Scorpia: the fancy looking header on the right bottom of the PCB is the wing adapter I/O header. The holes inbetween the pins are for standoffs to give wing boards more stability.

@ladyada: hmmm, I can see your point. On the Eagle schematics it says: "this work is licensed under the Creative Commons NONCOMERCIAL License" - yes there is a typo! ;)

/EDIT

Eventhough noncommercial is certainly a restriction (and would apply to anyone producing and selling the design) making it not completely open, I am not sure if Ian and Jack have come to a final decision under what kind of license they will release the design once it is completed. ;)

/END EDIT

@Jack: nice to see the 16-bit transceiver instead of the 8-bit buffer ... makes it even more versatile now. ;)

I prefer the numbering to start with '0' as this seems to be the most commonly used notation for data and address busses in data sheets and designs - at least I am more used to it and it will make referencing easier when using the SUMP client.

[RichF]

Jack. Looks good to me,  I wish you could have found room for the Res pads ,
I noticed the Dir pins on the buffer IC  were not routed , I hope you plan to control them with the FPGA

I prefer to start with 0 but no great conviction.

[RichF]

Jack question was concern for the added length because of the 10x10cm limit imposed by Seeed's Fusion promotion?