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Topic: FPGA Verilog "Demon Core" + AdvTrigger + Meta + RLE + Timing (Read 160607 times) previous topic - next topic

Re: FPGA Verilog Port + AdvTriggers + Meta + RLE + Timing Fi

Reply #15
Mine has the same error. I am doing a capture on it now.

Test:

Upload verilog bitstream
Upload v2.1 FW
Send 0x02 in Hercules, get 1ALS
Upload v2.3 FW
Send 0x02 in Hercules, get no reply

Verified for good measure.

Test bench is attached.
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Re: FPGA Verilog Port + AdvTriggers + Meta + RLE + Timing Fi

Reply #16
rsdio, the fpga never actually runs at 200Mhz.  It performs double-data-rate sampling at 100Mhz to capture 200Msamples/sec.  It actually has a better-than-ever chance of actually doing that now.  :-)

Ian, I've hooked a scope & the only difference I see is on MOSI.  With the dynamic_depth bitfile, MOSI behaves differently than with my bitfile.  MOSI is the output from the PIC, so something is up there.

Assuming the client is trying to write 0x02 (the Query ID) command, with dynamic-depth.bit, MOSI is initially high & is left high afterwards:
Code: [Select]
 SCLK:  0000000011100011100011100011100011100011100011100011100000000
 CS:    1110000000000000000000000000000000000000000000000000000000111
 MOSI:  1111110000000000000000000000000000000000011111100000011111111
With my bitfile, MOSI is initially -low-, and remains low afterwards:
Code: [Select]
 SCLK:  0000000011100011100011100011100011100011100011100011100000000
 CS:    1110000000000000000000000000000000000000000000000000000000111
 MOSI:  0000000000000000000000000000000000000000011111100000000000000

Under simulation, my fpga immediately asserts "dataReady".  Nothing happens here.
It's almost as if the fpga is stuck in reset, or the dataReady pin is being held down. 

I'm going to make a test image to pulse one of the LED's at a slow rate.  A sign
of life heartbeat next...

-- IED
-- debugging hardware at 2am is a bad idea...

Re: FPGA Verilog Port + AdvTriggers + Meta + RLE + Timing Fi

Reply #17
Tied it up to a LA, and sure enough the PIC sends properly but never gets a dataready reply.

Questions:
1. Is dataready ok - is it setup and an  input on the PIC? (seems like yes)
2. Is the ROM held in reset (yes, did a logic check)
3. Is it something during the setup phase - does the PIC engage the pins differently. I'll get these captures now.
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Re: FPGA Verilog Port + AdvTriggers + Meta + RLE + Timing Fi

Reply #18
Looks like we posted at the same time. I'll capture the dynamic one now for comparison
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Re: FPGA Verilog Port + AdvTriggers + Meta + RLE + Timing Fi

Reply #19
I'm posting this for comparison. This is v2.3 firmware with 2.12 bitstream. I'll try with v2.1 now too.

The MISO is high at beginning and end.

MOSI stays high between 0x02 and reading the data too.
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Re: FPGA Verilog Port + AdvTriggers + Meta + RLE + Timing Fi

Reply #20
Found it.  Problem in my spi_receiver.  Something about the 2.3 firmware was managing to confuse it.  It's more robust now, and works!!!

Whew!  Must be something to that "third-times-the-charm".

Is there any way to go back & edit the first posting to use this attachment?  The old board used to allow editing, but this one doesn't.

-- IED
-- debugging hardware at 2am is a bad idea...

Re: FPGA Verilog Port + AdvTriggers + Meta + RLE + Timing Fi

Reply #21
Fantastic! I still wonder what the difference is. When you have a new synthesis I'd like to give it a spin under debug.

-------------
I attached teh v2.1-dynamic above. Here si what I can tell:
1. Dynamic bitstream always has MISO high at start and finish. Both verilog tests always have MISO low (at start and finish).
2. Dynamic bitstream always has MOSI high between writing and the next read. The verilog version has it low in both cases.

I guess the question is - who is holding what high when, and to whom does it matter. I'll runt he PIC under debug and check the registers to be sure.
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Re: FPGA Verilog Port + AdvTriggers + Meta + RLE + Timing Fi

Reply #22
Thanks for letting me know about the edit issue, everyone should be able to edit their posts. I'm still getting it figured out.
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Re: FPGA Verilog Port + AdvTriggers + Meta + RLE + Timing Fi

Reply #23
[quote author="dogsbody"]rsdio, the fpga never actually runs at 100Mhz.  It performs double-data-rate sampling to capture at 200Mhz.  It actually has a better-than-ever chance of actually doing that now.  :-)[/quote]I was aware of that, thanks to the excellent hardware documentation of the OLS from Jack and Ian.  However, I didn't realize that you were talking about the clock frequency of the FPGA as opposed to the sample rate of the OLS function.  Now that I think about it, you're saying that your new FPGA configuration is so efficient that you could overclock the chip to 105 MHz and it would still work (meaning the 200 MHz sampling would be running at 210 MHz).  Fantastic!

(P.S. I wrote Fantastic! before Ian's post came through...)

Re: FPGA Verilog Port + AdvTriggers + Meta + RLE + Timing Fi

Reply #24
The edits should be fixed. I see you attached a new version - sorry, I'm one step behind. The 'new message' warning didn't show that there was a file attached. I'll test now.
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Re: FPGA Verilog Port + AdvTriggers + Meta + RLE + Timing Fi

Reply #25
Verilog v3 + v2.3 is attached. It looks just like the successful verilog before (unlike dynamic nothing is high)

On reflection - while I'm very confused about the difference between v2.1 and v2.3 caused the issues, I do remember a 'problem' with the (FPGA) SPI module. I was using SUMP core in another project and I had to ensure that MOSI (?) was high in idle or there were various problems (no data, dataready stuck with, etc). That does not seem to be the case here.

I have one more idea for a test to try.
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Re: FPGA Verilog Port + AdvTriggers + Meta + RLE + Timing Fi

Reply #26
[quote author="rsdio"]you're saying that your new FPGA configuration is so efficient that you could overclock the chip to 105 MHz and it would still work (meaning the 200 MHz sampling would be running at 210 MHz).  Fantastic![/quote]
Thanks, and Yes! 

It's actually even better than that...  I'm forcing the tool to assume clock jitter of 1ns, in addition to requiring the 105Mhz.  Without the jitter setting, it'd hit 120Mhz easy.  Not a good idea though to remove the jitter constraint.

btw, without the advanced trigger the fpga would hit 150Mhz easy (or 300 DDR Msamples/sec).

All that logic does slow thing down...  <sigh>  :-)
-- IED
-- debugging hardware at 2am is a bad idea...

Re: FPGA Verilog Port + AdvTriggers + Meta + RLE + Timing Fi

Reply #27
I ran some tests without the FPGA in the loop. I booted as normal, test the 0x02 reply, then placed a jumper over PGM to hold the FPGA in reset. I attached dataready to ground through a 1K resistor to stop random data.

I did two tests:
1. I connected the MOSI and MISO pins to ground with a 1K resistor. The Saleae stays high when a pin is floating, so I wanted to tell the difference between floating and ground. Here you can see that MISO stay low before/after EDIT: MOSI is high before and low after...
2. Left all pins floating. Here MISO (floating) is high as expected. What is strange is that MOSI is also high at the end of the 0x02 write. Since it is low with the resistor, I have to guess the PIC is floating MOSI between bytes. That doesn't make any sense though.

Is there any kind of bus keep or pullx on your pins?
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Re: FPGA Verilog Port + AdvTriggers + Meta + RLE + Timing Fi

Reply #28
[quote author="ian"]Is there any kind of bus keep or pullx on your pins?[/quote]
Not to my knowledge.  I avoided changing the I/O's, except for the addition of timing constraints. 

I'm off to bed now.  Shall pick this up tomorrow.  Cheers!
-- IED
-- debugging hardware at 2am is a bad idea...

Re: FPGA Verilog Port + AdvTriggers + Meta + RLE + Timing Fi

Reply #29
I made a new firmware with the SPI LAT pins being set instead of the PORT pins. Technically writes to PORT are supposed to go to LAT, but sometimes the compiler is stupid.

No, during setup, the SPI outputs are configured through LAT instead of PORT. The PPS is supposed to handle all of that when it is configured.

That seems to fix it with the Verilog 2.

I loaded the v2.12 bitstream to test that, it seems to be compatible. You can see in the LA output attached that it still doesn't match the Verilog version.

Is it possible that the Verilog version holds MISO low even when CS is high?

I can't explain MOSI being high between 0x02 and reads on one and low on the other.
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