Skip to main content
Topic: Up to 60MHz 8bit logic analyzer (Read 19344 times) previous topic - next topic

Up to 60MHz 8bit logic analyzer

I got me a FT2232H Mini-Module some time ago as I wanted to test the high speed chip mostly because the spec show that this chip can do in hw what buspirate does in sw... What got me interested is it's FT245 synchronous mode - darn thing is bloody fast and today I finally found some time to check it out.

I whipped up a small program (tested on linux, uses openGL (glx) to display data, no idea if it can be compiled on windows but if you have cmake it might work - I don't have windoze to test it - I will attach source in a sec, not that it is something revolutionary :D it's few hours of coding only)....

How does it work? First you must use FT_Prog to set your A channel to FT245 hw. When this mode is turned on the B channel stop working as all resources are used by FT245 on channel a.

FT245 allow read or write to be performed. In the write mode (from the external hardware point of view, so you are writing to ftdi chip, hence your computer is reading from the DUT) the 2232h produces 60MHz clock on the CLKOUT pin (AC5 pin). When ready to receive 2232H will lower the TXE (AC1) pin down (the pin will go high if you don't read the data from the 2232H so it's buffers fill up) and it will get it back high if it is unable to receive data. The data on AD0-AD7 will be written to 2232H on every CLKOUT clock when WR (AC3) pin is low. For the test I shorted TXE and WR pins so that data is read on every CLKOUT hence having 60MHz readout of the 8 data bits on the AD.

In order to change scanning speed an additional circuit would be required so that WR pin can be triggered on every N'th CLKOUT. A small CPLD capable of running at 60MHz would be great choice. Anyhow, with fast enough client we can exctract data at whatever speed below 60MHz we want, it is just matter of processing 8bit wide stream :)

Re: Up to 60MHz 8bit logic analyzer

Reply #1
Fantastic!

Quote
For the test I shorted TXE and WR pins so that data is read on every CLKOUT hence having 60MHz readout of the 8 data bits on the AD.

Can this be done without the hardware connections? I'm playing with the FT2232+CPLD Bus Blaster v2 board here:
http://dangerousprototypes.com/forum/in ... pic=1490.0

Since the CPLD can be a pass-through, or even make any extra connections like described above, I want to make sure we connect any important FT2232 pins to the CPLD so creative new uses like this are possible.
Got a question? Please ask in the forum for the fastest answers.

Re: Up to 60MHz 8bit logic analyzer

Reply #2
you have to pull the WR pin down in order for byte to be read by FTDI..

The thing is - there's two ways to pull the status, you can do it using BitBang option but max speed I managed to achieve with this was bit over 4KHz so pretty useless, now the FT245 synchronous mode actually works like protocol, so you don't scan pins but you read then like they are coming via serial port (with ft_read() ) so if WR pin is not down 2232H is waiting for input ... pulling it "permanently down" would make it work all the time but I don't see the problem of adding some way of shortening this "on demand" ... just, you can't do it from ftdi ... in theory you can

1. set 2232H to bitbang mode or serial mode or whatever your "other device on board talk"
2. communicate with some device on board to "setup whatever, including the "drop the WR pin"
3. reset 2232H to FT245 mode
4. go crazy ...

but it is imho much easier to put a jumper on board that will pull WR to GND :) and add a red led on TXE so if TXE is high - you have red led meaning "we are not receiving" and possibly green led in reverse that will light up when TXE goes low -> we are ready to receive :D

Re: Up to 60MHz 8bit logic analyzer

Reply #3
All of the needed pins are already connected to the CPLD, but for example I'll try to connect AC5 to a GCK pin.
Got a question? Please ask in the forum for the fastest answers.

Re: Up to 60MHz 8bit logic analyzer

Reply #4
you should really add .gz and .bz2 as allowed extensions, the forum just ate mu long post :(

inside zip:
ftditest4.tar.bz2  - project source, kdevelop4 + cmake (if you are using 32bit system replace the library in the ftdi directory)
ftditest_static.tar.bz2 - binary (ftdi d2xx statically linked, 64bit binary compiled on Fedora13, should work on any 64bit linux with opengl)

movie: http://www.youtube.com/watch?v=UvtFJ50bCho (unfortunately my screen capture app captures only 10fps, it looks much better in real life)

mouse - click+move, rotate
wheel - go trough data (1/3 of page if with shift)
ctrl + wheel - zoom
middle button + move - pan left/right

q - quit
esc - quit
space - start/stop scanning

Re: Up to 60MHz 8bit logic analyzer

Reply #5
[quote author="ian"]
All of the needed pins are already connected to the CPLD, but for example I'll try to connect AC5 to a GCK pin.
[/quote]

AC5 is clock out yes, might be cool to go as clock on cpld but note that it is clkout only in FT245 mode ... but all in all you only have to worry about 3 pins :D (other then 8 data pins)

Re: Up to 60MHz 8bit logic analyzer

Reply #6
here's just a small CLI that will open FT245 and read data .. (64bit linux binary and source)

Code: [Select]
[arhimed@luckey build]$ ./ftdiCLI -h
./ftdiCLI [<length> [<flush>]]
<length> If specified defines number of bytes to fetch from 2232H
default value is 100000000
<flush> If specified defines after how many bytes to flush output

[arhimed@luckey build]$

Re: Up to 60MHz 8bit logic analyzer

Reply #7
There is something strange/wrong here !

You say that you read the 60 MHz clock signal from the FT2232 chip. It's impossible!
on the specifications of the chip, it's said to go up to 30MBps in synchronous mode. So how can you achieve reading at 60Mhz.
Second thing you have to notice, is that this chip does HighSpeed USB, so it's USB bandwidht is , limited to 480Mb/s (60M Byte/s), this includes all data, i.e even the protocol header data and all other related data, and this is in best case (i.e. usb port 100% free bandwidth and fast enought PC).

I think that you only does sampling at 15 to 20 (max) MHz, and the fact that you used a true square signal so you cannot see "gaps" between signals and you are sampling at more spaced times, but since ur test signal is square, you got read true square signal without ovelapping or gaps.

Just thoughts !!! need to be verified. Try to generate a 20MHz or so signal with a signal generator (an AVR at 20Mhz can do it or a PIC32 ) and generate signals with variation in the chronograms width (like with PWM), and try to sample with OpenLogic Sniffer at 50Mhz and with the FT2232 and compare obtained data.

Regards

Re: Up to 60MHz 8bit logic analyzer

Reply #8
[quote author="octal"]
You say that you read the 60 MHz clock signal from the FT2232 chip. It's impossible!
on the specifications of the chip, it's said to go up to 30MBps in synchronous mode. So how can you achieve reading at 60Mhz.
[/quote]

Read the specification again. It is able to do 60MHz with one channel or 30MHz with two channels.

Here's the snippet from data sheet:
Quote
This single channel mode uses a synchronous interface to get high data transfer speeds. The chip drives a 60MHz CLKOUT clock for the external system to use.

AN130:
Quote
1 Introduction
This application note illustrates how to set the FT2232H into an FT245 Style Synchronous FIFO mode. If the requirement is to transfer data at 60MHz, and the data rate must greater than 8MB per second, then the FT245 Style Synchronous FIFO mode is the best solution. The FT2232H only channel A can be configured as a FT245 style synchronous FIFO interface. When configured in this mode, channel B is not available as all resources have been switched onto channel A.
Note : This mode is only available with port A of FT2232H device.

unfortunately I don't have a scope nor generator that can do 60MHz to test it and I only have a single 2232H chip so cannot use two of them to "talk" so I can measure speed... but if I read documentation (especially AN_130) correctly if you read from the ft2232H's buffer fast enough it will fetch data on every clock, the only time when the TXE will be high (not ready to receive data) is if buffer is full.


Re: Up to 60MHz 8bit logic analyzer

Reply #10
bin quite busy ... the code generating the pulse is (pic32mx)

Code: [Select]
...
    SYSTEMConfigPerformance(80000000L);
...
    while(1){
        LATDbits.LATD0 = 1;
        LATDbits.LATD0 = 1;
        LATDbits.LATD0 = 0;
        LATDbits.LATD0 = 0;
        LATDbits.LATD0 = 0;
    }
...

I scanned the result with 50MHz OBLS and with 60MHz 2232H and "scewed" results to match

Code: [Select]
...
fprintf(f, "%i, %i, %in", i, b50[i*5/6], b60[i]); //b50 is 50MHz from OBLS, b60 is 60MHz from 2232H
...

and the result is


Re: Up to 60MHz 8bit logic analyzer

Reply #12
i did some research on this. I have the busblaster v2, and I have created simple 8bit counter, and some glue logic on the TXE and WR pins.

One minor problem is that AC5 is not on GCK. But the timing report says that the clock should be fine up to 200mhz.

libftdi-1.0 (git version) has stream test application, that reads as fast as it can. I have modified it to check adjacent bytes for difference larger then 1. It seems that it keeps loosing quite a lot data! So 60Mhz might not be real at all.

I will try later with 30mhz, but the clock not on GCK makes it harder as i cannot use cpld's internal clock divider.

Re: Up to 60MHz 8bit logic analyzer

Reply #13
Sorry about that. I did make a version like that, but the clock trace had to go under all the other traces and i prefered to make it straight and short to hedge against noise issues.

Maybe we can revisit it in v3.
Got a question? Please ask in the forum for the fastest answers.

Re: Up to 60MHz 8bit logic analyzer

Reply #14
[quote author="robots"]
It seems that it keeps loosing quite a lot data! So 60Mhz might not be real at all.
[/quote]

I tried similar thing and in 10M test I had only a single byte lost .. I was reading with my cli app that uses proprietary driver from ftdi and reads into ram ..

I think the async transfer with a small buffer is much better idea