Re: Status of RLE
Reply #11 –
It might be a good idea to have an easy way of selecting an internal signal generator in the FPGA as signal source, for debugging purposes.
You just need to send 0x03 to the serial port, then it goes into signal generator mode which can be bridged from the buffer to the wing header. Probably not as simple as it could be, but it's already there. I believe Jawi's client can send 0x03 to trigger the test, could be wrong though.
The test can also be trigger by a jumper on the UART header, but you can use anything to temporarily connect it at startup - foil, gum wrapper, small piece of wire, etc.