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Topic: Pirate V3.6 fw5.10 can't see clock SPI (Read 639 times) previous topic - next topic

Pirate V3.6 fw5.10 can't see clock SPI

Hi folks is there any way to manipulate the clock manually? The only reason I ask is that I am attempting SPI comms, and using SIGROK to read the outputs. I get CS ok, along with MOSI but no clock! Self-test passes ok. Something is odd for sure.
When I put the PIC back in that produces the SPI data for the CCT I can see all outputs so there is clearly something at odds with the bus pirate? Oh I am using hiZ with 5v pullups too.

Re: Pirate V3.6 fw5.10 can't see clock SPI

Reply #1
Please Ignore, I forgot pullups :-/

Re: Pirate V3.6 fw5.10 can't see clock SPI

Reply #2
Hmm, so it is working, however, I have a couple of questions. Firstly, why is there such a long space between CS changing state and data/clock starting, and between bytes of data too? I am not asking to look at the response from the SPI chip. Also, would it be possible to change things so that data is changed mid-clock instead of on a clock change? I think this would be much better for stability at high speeds?

Thanks

 

Re: Pirate V3.6 fw5.10 can't see clock SPI

Reply #3
The delay is due to the Bus Pirate pushing out the display text between bus operations. This is a major limitation of the design, and we are correcting it by adding a FPGA to a new "Ultra" version.

You can adjust the clock and data polarity, phase, etc during setup. I believe you can choose from mid clock or falling/rising edge.
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