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Topic: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :) (Read 3419 times) previous topic - next topic

Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)

Reply #45
In terms of price, this is not gonna be in the 30 to 50 range until we move to a cheap Chinese SoC. There are probably $50 of parts on the board plus a 4 layer PCB and the whole thing has to be certified and probably shipped in a case.
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Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)

Reply #46
I'm curious why we couldn't support the JTAG auto detect?
I have a router with 20 pin header which should be a jtag, has not standard pinout, I tried many "jtag finder" none has had success.
All devices which I've seen, have more than 8 pins: 30, 24. So with only 8 pins I don't know how bus pirate detect all pins.

I'm sure we can do that.
Good...  :D

Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)

Reply #47
That's an interesting use case, and not one I'm familiar with. No we would not be able to probe 20 pins at once. I don't see how we get more than 8 IO with the current design. But we can definitely probe an 8 pin header :)
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Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)

Reply #48
Very interesting project. It has many pins, I think the new bus pirate must have at least 16 I/O pins, 32 is better.
The Glasgow revC, the one that will be manufactured first, has 16 pins (2 ports of 8 pins each). There will be a revD with 32 pins in the future. This makes it easy to do not only the JTAG scanning you mentioned, but also interface wide parallel busses, use it as a wide bus logic analyzer, read/write parallel EEPROM or flash,...

Another interesting function is "automatically determine unknown JTAG pinout", with new bus pirate is very hard add it.
Not has uC ARM, but a 8051, I don't know which is better.
The point of using the Cypress FX2 is not the 8051 core that is embedded, but that it offers really fast usb transfers from the FPGA. I get around 340 MBit/s of real data througput when running the transfer benchmark on my Glasgow prototype. The STM32F103 on the BusPirate Ultra can only do USB FullSpeed (12 MBit/s theoretical max.). Even STM32F4 with a separate ULPI PHY don't get near the transfer rate of the Cypress FX2.

The Glasgow and BusPirate Ultra have a bit of a different concept there: the BusPirate Ultra will usually do the processing and data conversion on the hardware, probably a smaller part in the FPGA and most of it in the STM32. The data is then transfered to the PC over a emulated serial port, with the same or similar protocol as the previous versions of the BusPirate. At least this is what I understood from Ian's posts here.

The Glasgow will instead usually use a custom software on the host PC. This software consists of Applets that configure the FPGA for the current task (gateware) and also a part that converts the data on the PC. So the 8051 microcontroller on the hardware has much less to do. Also the FPGA gateware is not a collection of generic pre-synthesized gatewares, but directly synthesized for the task and configuration at hand, making it more efficient. The downside is that you need to install the Glasgow software stack (Python, nMigen, Yosys, nextpnr) on the host PC, while the BusPirate just needs a USB CDC serial driver.

I hope the price will not be more than 50$.
The price for the Glasgow will probably be in the $150-$200 range. It will be available from here soon: https://www.crowdsupply.com/1bitsquared/glasgow

Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)

Reply #49
@electroniceel It is an absolutely killer project! You do really good work!

We're going to add a second USB bulk end point for non-terminal stuff that basically just gives access to the FPGA registers and FIFO, but it will never come close to the speed you get with the FX2. That's going to tear through some flash chips :)
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Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)

Reply #50
X

v1c is technically done, but we came up with some hot last minute additions. We'll probably skip this board and send out the updated version with the additional features at the end of the week.

New in v1c:
  • 4 layer PCB
  • 1MHz 12 bit SPI ADC connected directly to the FPGA
  • Vout/Vref is also measured through the analog mux, which was moved to the bigger 16bit version. This will probably change back to 2 x 4051s instead because supplies of the 74hct4067 are tight! Instead we'll have one "divide by two" 4051 for 5volt measurements on the IO pins, and 1 3.3volt 4051 tied directly to the ADC
  • Beefier 3.3volt supply, and 1.2volt supply is now monitored by the MCU for self test
  • 0.5mm flex cable connector for the display board
  • Additional ADC measurement before the back-current shut down on power supply. This will let us test the feature and also detect when it happens.
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Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)

Reply #51
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Wheee! I believe this is the first full test of the "Ultra" design with an actual device under test. In this case I used a 25LC020A SPI EEPROM that was already on a breadboard. Getting the loops and statemachines figured out was the most time intensive part of the "Ultra" firmware so far, at least for me. Now that we have a working framework, I think things will progress really fast from this point.
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Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)

Reply #52
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Couple updates to the firmware:
*SPI "r" command working
*Flipped LCD 180 degrees so we are pushing characters from left to right, instead of backwards
*Mode labels are written on mode changes (requires a full screen refresh which is annoyingly slow) this should be updated to use DMA
*Cleaned up LCD drawing functions
*Increased all SPI speeds to maximum
*Updated Bus Terminal logic analyzer with same color codes as the bus pirate ultra pinout

Todo:
*Use file system to load FPGA and LCD between modes
*Test I2C peripheral
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Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)

Reply #53
As much as possible, we'd like to move control of hardware to the FPGA so that everything can be controlled from the state machine command pipeline. In v1c we moved the voltage measurement to the FPGA by adding an SPI ADC. In a future revision it would make sense to move a few other things to the FPGA:

  • Pull-up resistor control
  • Vreg enable
  • Vreg margining (DAC)
  • v1d stuff

For debugging and self-testing we need to keep some redundant connections to the MCU as well, but primary control should be through the FPGA.

I had a look at replacing the DAC in the MCU with a small SPI DAC. Here's what I found:

MCP4902 8bit dual DAC TSSOP14
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MCP4902 seems to be a classic Microchip part, available at Mouser for $0.99 in 100s. However, the smallest package size is TSSOP14, and a quick check of SZLCSC shows they only have the SOIC version with 17 pieces in stock. That's not a great sign.
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Each update of a DAC takes 16bits, maximum speed is 20MHz.

MCP48FVB02 8bit dual DAC MSOP10

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MCP48FVB02 appears to be a part Microchip acquired when they bought Micrel. It comes in an MSOP10 package which is minor improvement over the MCP4902. It's a bit cheaper at $0.90 for 100pcs at Mouser. It's not stocked at SZLCSZ, which is a huge warning sign. Microchip Direct is really good about delivering parts in China if need be, but they can only deliver 1200 today and new stock won't be available until February (three and a half months away).

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It uses a 24bit command, which is a full byte longer than the MCP4092. Both the MCP4092 and MCP48FVB02 operate at maximum write speeds of 20MHz, so the MCP4092 will have a significantly higher maximum update speed.

DAC082S085CIMM/DAC084S085CIMM 8bit dual/quad DAC MSOP10
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Here's where it gets a bit interesting. DAC082S085CIMM is a dual 8 bit DAC from Texas Instruments, available for $1.24 in 100s at Mouser. SZLCSC only has 8 in stock for around $2 in 100s (13.20RMB). Low stock is bad news, and a higher RMB price than USD price that points to a limited stock or specialty chip to avoid (eg not something with high demand in China).

However, the DAC084S085CIMM is similar but has 4 DACs. We could use the extra DACs to add more programmable output power supplies, or a simple analog signal generator on a few of the IO pins. It's available at Mouser for $1.58 in 100s, and at SZLCSC for $1.15 (8.68RMB) with 1700 available and 1300 shipped in the last month. That's several good signs: it's cheaper than the 2 DAC version ($2 vs $1.15), RMB price is cheaper than USD price, and there is a fair amount of stock and turnover at SZLCSC which means it's actually being used in production. This seems like a good candidate. Just to further verify, there are 50K in stock at the TI store, and 20K in stock at Digikey for a slightly higher price.

X

The update command is 16bits, but where it really shines is the 40MHz maximum update speed (twice as fast as the Microchip DACs).




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Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)

Reply #54
X

2 inch display carrier board for Ultra v1d:
*Uses 10 pin 0.5mm flexible PCB connector, wired to the main board with a 1:N connection. This connector is much smaller and thinner than the 1.25mm connector on v1b, it reduces the space needed between the display board and the main board.
*Flipped LCD orientation 180 degrees so font data can be written into bounding boxes in a more natural “left-to-right” orientation, eliminating the need to precalculate the text end point and write characters in reverse sequence
*Nudged the display towards the IO header. We’ll experiment with some buttons in the remaining available space
*Decoupling capacitors on LCD power pins

X
2.8 inch display carrier board for Ultra v1d (in progress, todo:)
*Add decoupling caps to power pins
*Add slot for display flexible PCB cable to reach the connector on the back
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Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)

Reply #55
Very neat project so far, looks like it will be able to compete with Saleae's Logic Pro series.

Regarding the ADC and DAC: have you thought about implementing those in the FPGA? There is a white paper about implementing and ADC in one of their FPGA's from Lattice [1]. The DAC can be as simple as a PWM with an RC filter.

[1]: https://www.latticesemi.com/-/media/LatticeSemi/Documents/WhitePapers/AG/CreatingAnADCUsingFPGAResources.ashx?document_id=36525

Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)

Reply #56
Very cool, thank you for the link. I will have to try both methods suggested in the app note just to be more familiar with the internals of the ADC.

The ADC speeds (15 and 50khz) are very low though. With the TI ADCs we can do 1msps or 2.5msps which is in DSO nano territory. Eventually we'll do a dual rail parallel ADC at 100msps, but not till we move to the bigger BGA FPGA chip.

The DAC side would be really easy with FPGA pin, agree. Since we're using two in the power supply system I'm quite worried about the noise though. The other two I'd like to put behind a op amp with shutdown and output analog waveforms on two IO pins. Noise is still an issue with the DACs though because they have almost zero PSRR.
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Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)

Reply #57
The ADC speeds (15 and 50khz) are very low though. With the TI ADCs we can do 1msps or 2.5msps which is in DSO nano territory. Eventually we'll do a dual rail parallel ADC at 100msps, but not till we move to the bigger BGA FPGA chip.

The DAC side would be really easy with FPGA pin, agree. Since we're using two in the power supply system I'm quite worried about the noise though. The other two I'd like to put behind a op amp with shutdown and output analog waveforms on two IO pins. Noise is still an issue with the DACs though because they have almost zero PSRR.

True, the sample rate of the ADC is quite lousy. But hey, it's basically free  :D

If you're worried about the PSRR of the PWM DAC you can run them through a buffer (e.g. inverter gate) powered from a reference.

I'm aware that these solutions are a bit of an oddity, as a cost saving of 3 USD won't make a big dent in you total BOM cost.

Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)

Reply #58
The DAC datasheet also suggests powering from a shunt reference to reduce noise. I've been considering moving the ADC and DAC to a 3.0V reference. That reduces voltage measurement range to 0-6volts instead 0f 0-6.6, which makes a lot of sense and gives more resolution in the most likely to be used range (5.0V and under).
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Re: Bus Pirate "Ultra" v1a & v1b with ICE40 and Icestorm :)

Reply #59
Change List v1e:
*All PSU control to FPGA
*Flash chip to soic8_208 so we can use 128Mbit flash
*Give some thought to replacing the 571/245 with something suitable to all the logic levels supported by the buffers (maybe something with two independent rails?)
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