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Topic: One or two ideas on the transceiver (Read 274 times) previous topic - next topic

One or two ideas on the transceiver

Hello everyone,,
I'm a software guy and pretty much a noob in hardware field (not even eqipped by now with any gear except the obligate Arduino) - but eager to do more and learn more in that area. Enough said there for a bad introduction... ;) --

I just stumbled upon the Logic Sniffer project the other day, quite impressed really, and was wondering, wether the specs would be sufficient to debug a 100MBit Base-T ethernet line. So I looked up the bitrate on wikipedia, where they say it's 125MBit on the line with some fancy encoding done (to attenuate the radio noise).
OLS seems to just so fall short of that (...it may also be not doable because it's a differential signal, AFAIR, but anyways).
So I figured, it must (for one) be the transceiver with its t_pd of 4.5ns, that gives that limit, looked around, if there are other parts that might just push that limit a little further. Somehow I got stuck on TI parts (but there may be other options). There's one over there, that fits the specs of the On Semi part spot on and claims a t_pd of 4ns (max) - which is not big, but in theory should give just 250MS/s (and thus the magic 125MHz ideally, no jitter).
>> SN74LVC16245A (I'm not allowed to link off-site atm).
To my surprise it is even pin-compatible (but that will be some trivial 74 CMOS standard thing I reckon). There are also other transceiver/buffer parts, that even get down to like 2ns but do not offer 5V tolerant Inputs and operatate from lower Vcc.
I don't have an OLS yet, but just wanted to pass that on as an idea, to maybe replace the On Semi with that thing on a bare side-wing pcb to see if it performs any better...?

My second fancy/weird idea along that transceiver line is this:
I've found the posting about EEVBlog here in the forum, mentioning that many folk dont't like the fixed H/L voltages on buffered, pure digital LAs like the OLS. Then there also was a thread with the idea of replacing the transceiver with a comparator, that goes in the same direction (if I got that right).
Just having read the specs in these transceiver datasheets an idea came to mind... if I understand the specs correct, the H/L thresholds on these things actually are not fixed but depend on Vcc (Low will be typically around 0.35*VCC, High 0.65*Vcc).
So... why not make Vcc variable!? (It goes down to 1.65V on the TI part, 2V for the On btw).
I have no idea, if that could be supplied from the FPGA directly - or the FPGA or MCU could control a linear regulator for the transceiver - or if all that makes any sense at all, but for sure, these levels are not fixed.
At the same time the maximum input tolerance should not suffer from this (up to about 6V - at least this data is given without condition in the tables). The output would give Vcc though, so the FPGA should be ablet to adjust to that.

This second idea too (if it is not complete nonsense) could be tested with a customized buffer-wing-shield (and adjusted FPGA bin). As said before, for now I have none of the necessary gear to go on with that, so this is just a vague idea I wanted to pass on.

Cheers,..