Hello All, I'm trying to read and write this EEPROM (<link removed due to spam measures, happy to provide it>)
I'm using a 93C56A, so it's 256x8 with no need to do anything with the ORG pin.
I've connected it thusly.
BP3 -> ROM
CS -> CS
CLK -> CLK
MOSI -> DI
MISO -> DO
+5v -> VCC
GND -> VSS
I'm a software engineer, but a self proclaimed electronics n00b, and this is my first time using the Bus Pirate in earnest, so I'm almost certainly making an elementary mistake, but I can't seem to spot it.
I've been reading through some threads that are similar, and trying to piece together the info into a working solution for myself.
I've read these;
viewtopic.php?f=4&t=5273 (http://dangerousprototypes.com/forum/viewtopic.php?f=4&t=5273)
viewtopic.php?t=665 (http://dangerousprototypes.com/forum/viewtopic.php?t=665)
viewtopic.php?t=510 (http://dangerousprototypes.com/forum/viewtopic.php?t=510)
I'm running a 3.a with the latest firmware I could find/use
Bus Pirate v3.a
Firmware v6.3-beta1 r2088 Bootloader v4.4
DEVID:0x0447 REVID:0x3046 (24FJ64GA002 B8)
http://dangerousprototypes.com
It passes self tests
HiZ>~
Disconnect any devices
Connect (Vpu to +5V) and (ADC to +3.3V)
Space to continue
Ctrl
AUX OK
MODE LED OK
PULLUP H OK
PULLUP L OK
VREG OK
ADC and supply
5V(4.98) OK
VPU(4.98) OK
3.3V(3.35) OK
ADC(3.31) OK
Bus high
MOSI OK
CLK OK
MISO OK
CS OK
Bus Hi-Z 0
MOSI OK
CLK OK
MISO OK
CS OK
Bus Hi-Z 1
MOSI OK
CLK OK
MISO OK
CS OK
MODE and VREG LEDs should be on!
Any key to exit
Found 0 errors.
I'm using 3 wire mode, with "default" settings
HiZ>m7
Set speed:
1. ~5KHz
2. ~50KHz
3. ~100KHz
4. ~400KHz
(1)>1
CS:
1. CS
2. /CS *default
(2)>2
Select output type:
1. Open drain (H=Hi-Z, L=GND)
2. Normal (H=3.3V, L=GND)
(1)>1
Ready
3WIRE>
When I read a new chip, I get all zeros
3WIRE>]0b110 _^_^_^ 0x00 r:10[
/CS DISABLED
WRITE: 0x06
DATA OUTPUT, 0
CLOCK TICKS: 0x01
DATA OUTPUT, 0
CLOCK TICKS: 0x01
DATA OUTPUT, 0
CLOCK TICKS: 0x01
WRITE: 0x00
READ: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
/CS ENABLED
I try to write to it with an EWEN -> Write -> EWDS, which seems fine..
3WIRE>]0b10011[
/CS DISABLED
WRITE: 0x13
/CS ENABLED
3WIRE>]0b101 _^_^_^ 0x00 0xab[
/CS DISABLED
WRITE: 0x05
DATA OUTPUT, 0
CLOCK TICKS: 0x01
DATA OUTPUT, 0
CLOCK TICKS: 0x01
DATA OUTPUT, 0
CLOCK TICKS: 0x01
WRITE: 0x00
WRITE: 0xAB
/CS ENABLED
3WIRE>]0b10000[
/CS DISABLED
WRITE: 0x10
/CS ENABLED
But it doesn't seem to take, or.. My reads are incorrect
3WIRE>]0b110 _^_^_^ 0x00 r[
/CS DISABLED
WRITE: 0x06
DATA OUTPUT, 0
CLOCK TICKS: 0x01
DATA OUTPUT, 0
CLOCK TICKS: 0x01
DATA OUTPUT, 0
CLOCK TICKS: 0x01
WRITE: 0x00
READ: 0x00
/CS ENABLED
Any guidance for a n00b? Apologies in advance that I'll likely ask you to explain acronyms and common terms, so feel free to direct me to links/manuals/guides.
Hi rgeyer.
I know nothing, but it seems to me you are using /CS while actually the chip where you are working on need CS.
Hence you have to set your Bus Pirate for it by choosing option 1 for the CS (chip select), do not the 2 which is the default.
That is stated also in the links you provided.
However here you go a couple of others that could be useful to you:
http://dangerousprototypes.com/blog/201 ... e-93lc46b/ (http://dangerousprototypes.com/blog/2013/12/20/bus-pirate-meets-the-93lc46b/)
http://bobdasquirrel.blogspot.com/2013/ ... lc46b.html (http://bobdasquirrel.blogspot.com/2013/01/bus-pirate-meets-93lc46b.html)
Be seeing you.
U.Sb
So, I'm beginning to think that my buspirate is actually just defective.
I picked up a logic analyzer, and hooked it up to the BP to see if I was sending the correct signals to the EEPROM.
The connections are:
Logic -> BP
D0 -> CS
D1 -> CLK
D2 -> MOSI
D3 -> MISO
D4 -> +3.3v
D5 -> +5v
The attached image is the result of the following command.
W]0b110 0 r:8[w
[attachment=0]
I'm using the voltage regulators as a rising edge trigger for my logic analyzer, because nothing else seemed to be engaging.
Here's some output from the BP itself turning on/off the CS voltage. I expect the bottom row to switch between "L" and "H" and for the CS pin to go high, but I don't see any difference. Am I misinterpreting the output from the BP "v" command?
3WIRE>v
Pinstates:
1.(BR) 2.(RD) 3.(OR) 4.(YW) 5.(GN) 6.(BL) 7.(PU) 8.(GR) 9.(WT) 0.(Blk)
GND 3.3V 5.0V ADC VPU AUX CLK MOSI CS MISO
P P P I I I O I O I
GND 0.00V 0.00V 0.00V 0.00V H L L L H
3WIRE>]
/CS DISABLED
3WIRE>v
Pinstates:
1.(BR) 2.(RD) 3.(OR) 4.(YW) 5.(GN) 6.(BL) 7.(PU) 8.(GR) 9.(WT) 0.(Blk)
GND 3.3V 5.0V ADC VPU AUX CLK MOSI CS MISO
P P P I I I O I I I
GND 0.00V 0.00V 0.00V 0.00V H L L L H
3WIRE>[
/CS ENABLED
3WIRE>v
Pinstates:
1.(BR) 2.(RD) 3.(OR) 4.(YW) 5.(GN) 6.(BL) 7.(PU) 8.(GR) 9.(WT) 0.(Blk)
GND 3.3V 5.0V ADC VPU AUX CLK MOSI CS MISO
P P P I I I O I O I
GND 0.00V 0.00V 0.00V 0.00V H L L L H
Hi rgeyer.
I am really sorry you have the problem you wrote.
In order to depth the matter you can try to do this:
viewtopic.php?f=4&t=7047#p60489 (http://dangerousprototypes.com/forum/viewtopic.php?f=4&t=7047#p60489)
In my opinion how you verified the thing it is not reliable because the result is also a function of the 93C56A.
However here are some of my thoughts:
1) With 3 WIRE protocol and as general rule with open drain/open collector, pull-up resistors are required but the log of your "v" command during the tests does not show any pull-up as VPU is always 0.00V.
http://dangerousprototypes.com/docs/Raw_3-wire (http://dangerousprototypes.com/docs/Raw_3-wire)
2) You have to use CS, do not /CS (ok, that your was only a test in order to trigger the logic analyzer so actually in the real scenario you would have used the recommended setting as I suggested you).
I believe your Bus Pirate is fine and the whole matter is due something weird in the settings.
Be seeing you.
U.Sb
U.Sb
Thank you for the input. After some patience, and trying a few other things, I was able to get this working.
I noted your comment about using CS instead of /CS, tho I had thought that was just reversing the polarity I.E. CS is idle low, and /CS is idle high. It seems that this setting actually determines if chip select is triggered at all?
At any rate, I'm able to communicate with the chip now, my BP hardware is not defective. Working on building out some python scripts to efficiently read/write these chips now.
Thank you!
HiZ>m
1. HiZ
2. 1-WIRE
3. UART
4. I2C
5. SPI
6. 2WIRE
7. 3WIRE
8. LCD
x. exit(without change)
(1)>7
Set speed:
1. ~5KHz
2. ~50KHz
3. ~100KHz
4. ~400KHz
(1)>4
CS:
1. CS
2. /CS *default
(2)>1
Select output type:
1. Open drain (H=Hi-Z, L=GND)
2. Normal (H=3.3V, L=GND)
(1)>2
Clutch disengaged!!!
To finish setup, start up the power supplies with command 'W'
Ready
3WIRE>W
POWER SUPPLIES ON
Clutch engaged!!!
3WIRE>[0b110 0x00 ^ r:256]
CS ENABLED
WRITE: 0x06
WRITE: 0x00
CLOCK TICKS: 0x01
READ: 0x40 0xE1 0x00 0x01 0xA7 0x0B 0x00 0x01 0x82 0x00 0x00 0x00 0x04 0x0E 0x00 0x01 0xA7 0x0A 0x00 0x01 0x82 0x00 0x00 0x00 0x04 0x0E 0x00 0x01 0xA7 0x0A 0x00 0x01 0x82 0x00 0x00 0x00 0x02 0x00 0x00 0x00 0x02 0x00 0x00 0x00 0x02 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x40 0xE0 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x98 0x69 0x98 0x69 0x98 0x68 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x40 0xE0 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x40 0xE0
CS DISABLED