Title: Bus Blaster update
Post by: ian on August 16, 2010, 01:57:02 pm
Post by: ian on August 16, 2010, 01:57:02 pm
This is a dirt-cheap high-speed JTAG debugger/flash programmer called the Bus Blaster. It was developed here:
http://dangerousprototypes.com/forum/in ... board=37.0 (http://dangerousprototypes.com/forum/index.php?board=37.0)
This project started clear back in the spring, but we could never get the buffers right for full 5volt-2volt interfacing. We finally decided some design was better than none, and designed this version that works from 3.3volts to 2.0volts. We could continue to struggle with the design forever, or if we build a less-than-perfect version there might be interest in improving the design from someone with the right insight.
The key here is that old FTDI2232 chip was 5volts, but the new H version is 3.3volts with 5volt tolerant pins.
We want 'out of the box' compatibility with the widely-supported olimex JTAG programmer, but the voltage difference was a real problem. The 5volt chip can be used with the AVC logic family to interface 5.0volts to 2.0volt targets, but when run at 3.3volts the maximum becomes 3.3volts max.
One way around this was using the LVC logic family, but we couldn't find chips that have output enable. That function would take an extra 5 individual output enable logic ICs...
This first version will be very simple - one IO header only, 3.3volts max; after we prove the design we can start to spice it up.
brd/cct images, Eagle files attached. Any suggestions and criticism are welcome.
http://dangerousprototypes.com/forum/in ... board=37.0 (http://dangerousprototypes.com/forum/index.php?board=37.0)
This project started clear back in the spring, but we could never get the buffers right for full 5volt-2volt interfacing. We finally decided some design was better than none, and designed this version that works from 3.3volts to 2.0volts. We could continue to struggle with the design forever, or if we build a less-than-perfect version there might be interest in improving the design from someone with the right insight.
The key here is that old FTDI2232 chip was 5volts, but the new H version is 3.3volts with 5volt tolerant pins.
We want 'out of the box' compatibility with the widely-supported olimex JTAG programmer, but the voltage difference was a real problem. The 5volt chip can be used with the AVC logic family to interface 5.0volts to 2.0volt targets, but when run at 3.3volts the maximum becomes 3.3volts max.
One way around this was using the LVC logic family, but we couldn't find chips that have output enable. That function would take an extra 5 individual output enable logic ICs...
This first version will be very simple - one IO header only, 3.3volts max; after we prove the design we can start to spice it up.
brd/cct images, Eagle files attached. Any suggestions and criticism are welcome.
Title: Re: Bus Blaster update
Post by: ian on August 16, 2010, 01:58:20 pm
Post by: ian on August 16, 2010, 01:58:20 pm
board
Title: Re: Bus Blaster update
Post by: ian on August 16, 2010, 02:02:26 pm
Post by: ian on August 16, 2010, 02:02:26 pm
I don't know why, but I'm having a really hard time attaching the CCT.
Title: Re: Bus Blaster update
Post by: ian on August 16, 2010, 02:14:32 pm
Post by: ian on August 16, 2010, 02:14:32 pm
The current buffers are:
74AVC4T245 and 74AVC2T45
We also tried (no output enable):
SN74LVC8T245
74LVC2T45
74AVC4T245 and 74AVC2T45
We also tried (no output enable):
SN74LVC8T245
74LVC2T45
Title: Re: Bus Blaster update
Post by: haley0918 on August 16, 2010, 04:09:03 pm
Post by: haley0918 on August 16, 2010, 04:09:03 pm
[quote author="ian"]
We want 'out of the box' compatibility with the widely-supported olimex JTAG programmer, but the voltage difference was a real problem. The 5volt chip can be used with the AVC logic family to interface 5.0volts to 2.0volt targets, but when run at 3.3volts the maximum becomes 3.3volts max.
[/quote]
Could you please elaborate further on this 3.3volts max problem?
We want 'out of the box' compatibility with the widely-supported olimex JTAG programmer, but the voltage difference was a real problem. The 5volt chip can be used with the AVC logic family to interface 5.0volts to 2.0volt targets, but when run at 3.3volts the maximum becomes 3.3volts max.
[/quote]
Could you please elaborate further on this 3.3volts max problem?
Title: Re: Bus Blaster update
Post by: tayken on August 16, 2010, 04:31:42 pm
Post by: tayken on August 16, 2010, 04:31:42 pm
Ian what about TXB0108? It is an 8 bit level translator with output enable. It might help maybe.
Title: Re: Bus Blaster update
Post by: ian on August 16, 2010, 04:33:53 pm
Post by: ian on August 16, 2010, 04:33:53 pm
The FTDI chip has 3.3volt output on the pins. If you connect that to a 2.5volt target the 3.3volt output is too much. If you connect it to a 5volt target, 3.3volt output isn't enough to register a high with the target. Also, some pins need to switch to high-impedance, and the FT2232 can't switch direction on the fly. So, we need a voltage buffer chip, one which translates between votlage, and also has an output enable for high-impedance outputs.
The trick is doing this at higher and lower voltages. The 74AVC4T245 has four level translating bits with output enable, but it is 3.3volts max.
The SN74LVC8T245 will do what we want 3.3v->(0-5), but it is a SOIC-only chip with 8 bits and a single OE channel.
74LVC2T45 is nice, but it only has direction switch and no output enable, a additional output enable buffer would be needed. This is probably the direction we'll go, with a 4066 or something, but we want to prove the programmer concept before messing with the buffers more.
The trick is doing this at higher and lower voltages. The 74AVC4T245 has four level translating bits with output enable, but it is 3.3volts max.
The SN74LVC8T245 will do what we want 3.3v->(0-5), but it is a SOIC-only chip with 8 bits and a single OE channel.
74LVC2T45 is nice, but it only has direction switch and no output enable, a additional output enable buffer would be needed. This is probably the direction we'll go, with a 4066 or something, but we want to prove the programmer concept before messing with the buffers more.
Title: Re: Bus Blaster update
Post by: ian on August 16, 2010, 04:35:49 pm
Post by: ian on August 16, 2010, 04:35:49 pm
Attached is the summary. The TSRST signal should be done twice: one signal as the input and the other as the output.
There are 6 outputs:
a) 3 - JTAG signals (TDI, TMS, TCK) with one output enable for all the signals
b) 1 - TSRST with OE
c) 1 - TRST with OE
d) 1 - DGBRQ
There are only 5 input signals:
a) TSRST
b) RTCK
c) TDO
d) DGBACK
e) VTG
Attached is a summary. Ignore the Vtarget detect connection, it was changed.
There are 6 outputs:
a) 3 - JTAG signals (TDI, TMS, TCK) with one output enable for all the signals
b) 1 - TSRST with OE
c) 1 - TRST with OE
d) 1 - DGBRQ
There are only 5 input signals:
a) TSRST
b) RTCK
c) TDO
d) DGBACK
e) VTG
Attached is a summary. Ignore the Vtarget detect connection, it was changed.
Title: Re: Bus Blaster update
Post by: ian on August 16, 2010, 04:40:09 pm
Post by: ian on August 16, 2010, 04:40:09 pm
We looked at the TXB chip, but it can only translate one way (meaning to higher or lower voltage targets):
Quote
VCCA should not exceed VCCB.
Title: Re: Bus Blaster update
Post by: tayken on August 16, 2010, 04:51:13 pm
Post by: tayken on August 16, 2010, 04:51:13 pm
[quote author="ian"]
We looked at the TXB chip, but it can only translate one way (meaning to higher or lower voltage targets):
Ahh, I see. I was just focusing on the part about 3.3 to 5v compatibility. But what we need is 2.0-5.0 output, am I right?
Just popped into my mind: An open drain buffer might solve the problem maybe? Found M54/74HC07 as an open drain buffer but no output enable. Maybe a FET switch can be used as a switch for enabling chip or not?
We looked at the TXB chip, but it can only translate one way (meaning to higher or lower voltage targets):
Quote
VCCA should not exceed VCCB.[/quote]
Ahh, I see. I was just focusing on the part about 3.3 to 5v compatibility. But what we need is 2.0-5.0 output, am I right?
Just popped into my mind: An open drain buffer might solve the problem maybe? Found M54/74HC07 as an open drain buffer but no output enable. Maybe a FET switch can be used as a switch for enabling chip or not?
Title: Re: Bus Blaster update
Post by: ian on August 16, 2010, 05:09:41 pm
Post by: ian on August 16, 2010, 05:09:41 pm
The 74LVC2T45 and SN74LVC8T245 are about perfect, except they don;t have individual output enables. just thinking about it today, writing the post, a 74HCT4066 analog switch might be perfect, or a CD4065 with a transistor switch if it's better to run at USB supply.
Title: Re: Bus Blaster update
Post by: tayken on August 16, 2010, 05:55:57 pm
Post by: tayken on August 16, 2010, 05:55:57 pm
Will USB alone be able to supply enough current? An SMD jumper might be a good idea for the test batch. If we find out that we have current issues with the USB, we can quickly unsolder the jumper and solder 2 cables for voltage source connection.
Title: Re: Bus Blaster update
Post by: LeissKG on August 16, 2010, 09:18:37 pm
Post by: LeissKG on August 16, 2010, 09:18:37 pm
Two back to back level translators should work. First translator goes from 3.3V USB device to 5V logic, the second translates 5V logic to any logic voltage between 1.2V and 5V ( for an Max3000 series translator).
Klaus Leiss
Klaus Leiss
Title: Re: Bus Blaster update
Post by: ian on August 17, 2010, 08:20:55 am
Post by: ian on August 17, 2010, 08:20:55 am
Quote
Will USB alone be able to supply enough current?
It should be, this version doesn't provide any power to the target board. That would probably be a good addition for a future board.
Title: Re: Bus Blaster update
Post by: rsdio on August 17, 2010, 10:11:25 am
Post by: rsdio on August 17, 2010, 10:11:25 am
[quote author="ian"]The SN74LVC8T245 will do what we want 3.3v->(0-5), but it is a SOIC-only chip with 8 bits and a single OE channel.[/quote]I realize that you're dealing with a few problems that are much bigger, but what's wrong with SOIC? They're actually my favorite these days...
Title: Re: Bus Blaster update
Post by: ian on August 17, 2010, 10:17:05 am
Post by: ian on August 17, 2010, 10:17:05 am
SOIC is my favorite too.
All outputs need to be enable-able to remove the programmer from the target. They can't be combined because there are 4 groups that need to be controlled separately. Each chip has one enable switch, and 4 of these chips are larger than the rest of the board :)
All outputs need to be enable-able to remove the programmer from the target. They can't be combined because there are 4 groups that need to be controlled separately. Each chip has one enable switch, and 4 of these chips are larger than the rest of the board :)
Title: Re: Bus Blaster update
Post by: Sjaak on August 17, 2010, 12:13:50 pm
Post by: Sjaak on August 17, 2010, 12:13:50 pm
I think Ian, more dislikes the only one OE..
Like ian just said :D
Like ian just said :D
Title: Re: Bus Blaster update
Post by: ian on August 17, 2010, 01:42:20 pm
Post by: ian on August 17, 2010, 01:42:20 pm
*The xtal should be changed to the same package as the Bus Pirate v4 (or vise versa)
Title: Re: Bus Blaster update
Post by: rsdio on August 17, 2010, 10:33:40 pm
Post by: rsdio on August 17, 2010, 10:33:40 pm
Which thread has the BP v4 schematics, PCB, and BoM?
Title: Re: Bus Blaster update
Post by: IPenguin on August 18, 2010, 02:31:33 am
Post by: IPenguin on August 18, 2010, 02:31:33 am
Bus Pirate v4 hardware (http://http://dangerousprototypes.com/forum/index.php?topic=727.0)
Title: Re: Bus Blaster update
Post by: rsdio on August 18, 2010, 03:03:23 am
Post by: rsdio on August 18, 2010, 03:03:23 am
Thanks for the link! I failed to look past the heading, which still says "v0a, v1a, v2 & v3."
Title: Re: Bus Blaster update
Post by: rsdio on August 18, 2010, 03:20:12 am
Post by: rsdio on August 18, 2010, 03:20:12 am
[quote author="ian"]
SOIC is my favorite too.
All outputs need to be enable-able to remove the programmer from the target. They can't be combined because there are 4 groups that need to be controlled separately. Each chip has one enable switch, and 4 of these chips are larger than the rest of the board :)[/quote]Ah, now I'm finally on the same page. I grabbed the latest Eagle files from the thread (thanks to IPenguin's link) and those SOIC chips are huge in comparison to everything else.
I'm wondering if there is some way to break the problem down into subsets that all work together. Instead of analog switches, perhaps individual FET switches could be used. Then the variable logic voltage could somehow be controlled by a separate circuit feeding a common voltage to all I/O header pins. I think the challenge is that FET gate voltages only work to turn on the FET if the signal voltages passing through the FET (source-drain) are not close to the gate voltage. If you're changing the logic level for each attached device, the gate voltages have to change as appropriate - or you could just pick a voltage large enough in magnitude that it would work in all situations.
Sorry I don't have more specific suggestions. Maybe I can look into this again later.
SOIC is my favorite too.
All outputs need to be enable-able to remove the programmer from the target. They can't be combined because there are 4 groups that need to be controlled separately. Each chip has one enable switch, and 4 of these chips are larger than the rest of the board :)[/quote]Ah, now I'm finally on the same page. I grabbed the latest Eagle files from the thread (thanks to IPenguin's link) and those SOIC chips are huge in comparison to everything else.
I'm wondering if there is some way to break the problem down into subsets that all work together. Instead of analog switches, perhaps individual FET switches could be used. Then the variable logic voltage could somehow be controlled by a separate circuit feeding a common voltage to all I/O header pins. I think the challenge is that FET gate voltages only work to turn on the FET if the signal voltages passing through the FET (source-drain) are not close to the gate voltage. If you're changing the logic level for each attached device, the gate voltages have to change as appropriate - or you could just pick a voltage large enough in magnitude that it would work in all situations.
Sorry I don't have more specific suggestions. Maybe I can look into this again later.
Title: Re: Bus Blaster update
Post by: IPenguin on August 18, 2010, 04:15:12 am
Post by: IPenguin on August 18, 2010, 04:15:12 am
[quote author="rsdio"]
Thanks for the link! I failed to look past the heading, which still says "v0a, v1a, v2 & v3."
[/quote]
You are welcome, Ian may want to change the headline to "v0a, v1a, v2, v3 & v4" and just move the "Bus Pirate v4 (private) (http://http://dangerousprototypes.com/forum/index.php?board=26.0)" child board there, too ;)
For the main subject (Bus Blaster update) I must admit that I don't see a way to solve all of Ian's problems without adding a CPLD/FPGA between the FT2232H and the actual JTAG interface ... what I am missing, too is the optional UART interface that should be available via the FT2232. The design has advanced well but got stuck at the point now where more complexity is required to keep it universal (supporting all voltage levels from 1,5V to 5V and the different interface implementations) or restrict it to support specific devices/families only. I am sorry but I don't have the time and the free mind to think up a (simple) solution right now ... still have to get to set up the FT2232H on a breadboard and check the behaviour of the MPSSE when switching pins from input to output and vice versa ... one problem is that the FT2232H mini module brings the pins out to two double-row headers ... so you can't plug it directly into a breadboard ... and I don't like to perform a "flying test" as I have one module only ...
Thanks for the link! I failed to look past the heading, which still says "v0a, v1a, v2 & v3."
[/quote]
You are welcome, Ian may want to change the headline to "v0a, v1a, v2, v3 & v4" and just move the "Bus Pirate v4 (private) (http://http://dangerousprototypes.com/forum/index.php?board=26.0)" child board there, too ;)
For the main subject (Bus Blaster update) I must admit that I don't see a way to solve all of Ian's problems without adding a CPLD/FPGA between the FT2232H and the actual JTAG interface ... what I am missing, too is the optional UART interface that should be available via the FT2232. The design has advanced well but got stuck at the point now where more complexity is required to keep it universal (supporting all voltage levels from 1,5V to 5V and the different interface implementations) or restrict it to support specific devices/families only. I am sorry but I don't have the time and the free mind to think up a (simple) solution right now ... still have to get to set up the FT2232H on a breadboard and check the behaviour of the MPSSE when switching pins from input to output and vice versa ... one problem is that the FT2232H mini module brings the pins out to two double-row headers ... so you can't plug it directly into a breadboard ... and I don't like to perform a "flying test" as I have one module only ...
Title: Re: Bus Blaster update
Post by: rsdio on August 18, 2010, 04:59:00 am
Post by: rsdio on August 18, 2010, 04:59:00 am
[quote author="IPenguin"]For the main subject (Bus Blaster update) I must admit that I don't see a way to solve all of Ian's problems without adding a CPLD/FPGA between the FT2232H and the actual JTAG interface ... what I am missing, too is the optional UART interface that should be available via the FT2232. The design has advanced well but got stuck at the point now where more complexity is required to keep it universal (supporting all voltage levels from 1,5V to 5V and the different interface implementations) or restrict it to support specific devices/families only. I am sorry but I don't have the time and the free mind to think up a (simple) solution right now ...[/quote]Very interesting that you should say this, because when I first looked at the "open" JTAG design from Texas Instruments, they invited people to alter the circuit, but warned that it would probably be a waste of time to attempt to remove the CPLD/FPGA from their design. The verdict with their design team was that the logic was just too complex to manage discretely.
This also has me wondering how they solved the multiple logic level problem - but I seem to recall that they have limited support there rather than a fancy solution.
This also has me wondering how they solved the multiple logic level problem - but I seem to recall that they have limited support there rather than a fancy solution.
Title: Re: Bus Blaster update
Post by: ian on August 18, 2010, 08:29:37 am
Post by: ian on August 18, 2010, 08:29:37 am
I like the idea of a CPLD too. Especially with the secondary MPSSE module it can be used to program/update the CPLD directly from the USB connection. One issue might be finding readily-available 5V cplds. Mouser stocks a ton of Lattice chips I'd like to check out, since the mini-multi programmer can program them :)
The H chip has a secondary UART channel and a secondary MPSSE module. They _must_ be broken out on a future design :)
Right now though, we're just determined to prove the concept on an actual PCB. That usually stimulates a ton of ideas, and unveils numerous problems with our initial assumptions.
The H chip has a secondary UART channel and a secondary MPSSE module. They _must_ be broken out on a future design :)
Right now though, we're just determined to prove the concept on an actual PCB. That usually stimulates a ton of ideas, and unveils numerous problems with our initial assumptions.
Title: Re: Bus Blaster update
Post by: Sjaak on August 18, 2010, 05:08:19 pm
Post by: Sjaak on August 18, 2010, 05:08:19 pm
[quote author="IPenguin"]
You are welcome, Ian may want to change the headline to "v0a, v1a, v2, v3 & v4" and just move the "Bus Pirate v4 (private) (http://http://dangerousprototypes.com/forum/index.php?board=26.0)" child board there, too ;)
[/quote]
I guess it is not accessable for everyone ;)
Ontopic: Something that comes to my mind is that voltage divider that is used for that logic analyzer that could be easily upgraded to the double amount of channels. It would only solve the input or use a simular thingg on the output?
the (original) article is here (couldn't find it fast on DP forums): http://openschemes.com/2010/03/27/zerop ... ication/2/ (http://openschemes.com/2010/03/27/zeroplus-logic-cube-the-modification/2/)
I would like a small cpld board too
You are welcome, Ian may want to change the headline to "v0a, v1a, v2, v3 & v4" and just move the "Bus Pirate v4 (private) (http://http://dangerousprototypes.com/forum/index.php?board=26.0)" child board there, too ;)
[/quote]
I guess it is not accessable for everyone ;)
Ontopic: Something that comes to my mind is that voltage divider that is used for that logic analyzer that could be easily upgraded to the double amount of channels. It would only solve the input or use a simular thingg on the output?
the (original) article is here (couldn't find it fast on DP forums): http://openschemes.com/2010/03/27/zerop ... ication/2/ (http://openschemes.com/2010/03/27/zeroplus-logic-cube-the-modification/2/)
I would like a small cpld board too
Title: Re: Bus Blaster update
Post by: tayken on August 18, 2010, 08:19:02 pm
Post by: tayken on August 18, 2010, 08:19:02 pm
Yeah, a CPLD might be the solution maybe. FTDI chip might use one of its ports to send messages to CPLD to enable, disable pins. But it might be left to v2, v1 might be used as a proof of concept or maybe just as a prototype for developers only. This might be a good place for me to start with CPLD's :D
Title: Re: Bus Blaster update
Post by: rsdio on August 18, 2010, 09:33:31 pm
Post by: rsdio on August 18, 2010, 09:33:31 pm
I hear you all on the "let's get something done as a proof of concept" ... but here's a wild idea: How workable is the existing Openbench Logic Sniffer as a way to test some JTAG ideas, assuming that you'll need some kind of FPGA anyway. There are 16 outputs available, right? Perhaps the OLS v2 would be better, unless the v1 is already communicating SPI direct between the PIC and FPGA.
Sorry - my ideas have been all over the place lately!
Sorry - my ideas have been all over the place lately!
Title: Re: Bus Blaster update
Post by: IPenguin on August 18, 2010, 10:05:16 pm
Post by: IPenguin on August 18, 2010, 10:05:16 pm
rsdio, your idea is not far off at all! I have been talking of designing a dual purpose LA/JTAG-adapter before and it makes complete sense.
When we looked at the USB MCU/controller for the OLS it came down to two options - a) FT2232D/H or b) PIC18F USB MCU. If we would
have chosen a FT2232, we would have ended up with a dual-purpose board or very close.
However, since most JTAG applications support FT2232 based (and proprietary) JTAG adapters only - actually they rely on the FTDI D2xx driver
and the FTDI JTAG DLL - using an OLS with a PIC USB MCU would not work for most applications or make it necessary to implement support
for the PIC based JTAG interface in the application (besides all the coding required on the PIC side, not to speak of all the details and information
that would be required and may not be readily available). Btw, on the OLS v1 the FPGA and the PIC already "talk" via SPI! But then speed is
important but not the only/real issue.
When we looked at the USB MCU/controller for the OLS it came down to two options - a) FT2232D/H or b) PIC18F USB MCU. If we would
have chosen a FT2232, we would have ended up with a dual-purpose board or very close.
However, since most JTAG applications support FT2232 based (and proprietary) JTAG adapters only - actually they rely on the FTDI D2xx driver
and the FTDI JTAG DLL - using an OLS with a PIC USB MCU would not work for most applications or make it necessary to implement support
for the PIC based JTAG interface in the application (besides all the coding required on the PIC side, not to speak of all the details and information
that would be required and may not be readily available). Btw, on the OLS v1 the FPGA and the PIC already "talk" via SPI! But then speed is
important but not the only/real issue.
Title: Re: Bus Blaster update
Post by: rsdio on August 19, 2010, 03:28:56 am
Post by: rsdio on August 19, 2010, 03:28:56 am
[quote author="IPenguin"]However, since most JTAG applications support FT2232 based (and proprietary) JTAG adapters only - actually they rely on the FTDI D2xx driver and the FTDI JTAG DLL - using an OLS with a PIC USB MCU would not work for most applications or make it necessary to implement support for the PIC based JTAG interface in the application.[/quote]If the FTDI drivers were open, then alternate drivers could be written to interface to the OLS. But that would require application support for selecting which driver is used. As you say, that would require details and information that may not be readily available.
Are there any tutorials on JTAG, especially the "standard" applications that are based on the FTDI driver and DLL?
On that note, is the FTDI JTAG DLL available on OSX? The driver is on OSX, but I don't see any documentation of the JTAG DLL on the FTDIChip site.
Are there any tutorials on JTAG, especially the "standard" applications that are based on the FTDI driver and DLL?
On that note, is the FTDI JTAG DLL available on OSX? The driver is on OSX, but I don't see any documentation of the JTAG DLL on the FTDIChip site.
Title: Re: Bus Blaster update
Post by: dpropicweb on August 19, 2010, 08:38:32 am
Post by: dpropicweb on August 19, 2010, 08:38:32 am
No sign of a DLL for OSX, but the source to the DLL is available at http://www.ftdichip.com/Support/Softwar ... Source.zip (http://www.ftdichip.com/Support/SoftwareExamples/MPSSE/FTCSPI/FTCSPI_Source.zip)
Title: Re: Bus Blaster update
Post by: ian on September 17, 2010, 03:46:52 pm
Post by: ian on September 17, 2010, 03:46:52 pm
This board just came in. There was a problem with IC6/7/8 footprints, the mask is on top of the pads.
That's OK, because I can sand it off and test out the circuit.
If we have to do another revision, we can probably use these for full 5.0-1.8volt level translation in the final version.
http://focus.ti.com/docs/prod/folders/p ... c1t45.html (http://focus.ti.com/docs/prod/folders/print/sn74lvc1t45.html)
http://focus.ti.com/docs/prod/folders/p ... c2t45.html (http://focus.ti.com/docs/prod/folders/print/sn74lvc2t45.html)
http://focus.ti.com/docs/prod/folders/p ... 8t245.html (http://focus.ti.com/docs/prod/folders/print/sn74lvc8t245.html)
That's OK, because I can sand it off and test out the circuit.
If we have to do another revision, we can probably use these for full 5.0-1.8volt level translation in the final version.
http://focus.ti.com/docs/prod/folders/p ... c1t45.html (http://focus.ti.com/docs/prod/folders/print/sn74lvc1t45.html)
http://focus.ti.com/docs/prod/folders/p ... c2t45.html (http://focus.ti.com/docs/prod/folders/print/sn74lvc2t45.html)
http://focus.ti.com/docs/prod/folders/p ... 8t245.html (http://focus.ti.com/docs/prod/folders/print/sn74lvc8t245.html)
Title: Re: Bus Blaster update
Post by: ian on October 07, 2010, 02:35:58 pm
Post by: ian on October 07, 2010, 02:35:58 pm
Finished soldering this yesterday, did the power up test just now. It powers and enumerates fine :)
There's two hold-ups on this design though
1 - the footprint for one of the buffer chips (IC6,7,8) had mask over the pads, so it will need to be scraped away to solder the buffer.
2 - since sending the design, we finally found the perfect 1.2volt-5.5volt buffer, if we have to revise anyways, we might as well test that.
Picture attached.
There's two hold-ups on this design though
1 - the footprint for one of the buffer chips (IC6,7,8) had mask over the pads, so it will need to be scraped away to solder the buffer.
2 - since sending the design, we finally found the perfect 1.2volt-5.5volt buffer, if we have to revise anyways, we might as well test that.
Picture attached.
Title: Re: Bus Blaster update
Post by: Crawford on November 11, 2010, 03:15:11 am
Post by: Crawford on November 11, 2010, 03:15:11 am
@Ian,
1. Is there a BoM for this version of the board (say if someone won a PCB and wanted to build it out :) ?
2. Have you hit up TI for samples of the sn74lvcXt45 buffers? Would they work on the current board?
-C
1. Is there a BoM for this version of the board (say if someone won a PCB and wanted to build it out :) ?
2. Have you hit up TI for samples of the sn74lvcXt45 buffers? Would they work on the current board?
-C
Title: Re: Bus Blaster update
Post by: ian on November 11, 2010, 08:42:22 am
Post by: ian on November 11, 2010, 08:42:22 am
The first post on this thread has the files for the Free PCB Sunday version, that should include part values:
http://dangerousprototypes.com/forum/in ... 75#msg8175 (http://dangerousprototypes.com/forum/index.php?topic=841.msg8175#msg8175)
There is some discussion of the buffer on the wiki:
http://dangerousprototypes.com/docs/Bus ... onnections (http://dangerousprototypes.com/docs/Bus_Blaster#JTAG_pin_connections)
The board can take the LVC or AVC version. I have the avc and lvc2t45, but there is no lvc version of the SN74AVC4T245 (or we'd have a perfect design!)
I will add the updated partlist to the wiki too by the end of the day.
http://dangerousprototypes.com/forum/in ... 75#msg8175 (http://dangerousprototypes.com/forum/index.php?topic=841.msg8175#msg8175)
There is some discussion of the buffer on the wiki:
http://dangerousprototypes.com/docs/Bus ... onnections (http://dangerousprototypes.com/docs/Bus_Blaster#JTAG_pin_connections)
The board can take the LVC or AVC version. I have the avc and lvc2t45, but there is no lvc version of the SN74AVC4T245 (or we'd have a perfect design!)
I will add the updated partlist to the wiki too by the end of the day.