Dangerous Prototypes

Other projects => Open Bench Logic Sniffer => Topic started by: busowner666 on April 09, 2016, 06:47:51 pm

Title: capture duration with OLS really short
Post by: busowner666 on April 09, 2016, 06:47:51 pm
Hi
I just acquired a logic sniffer for personnal fun.
So i took a board with a winbond SPI flash and wire it to the sniffer; then i lauched ols (from AUR Arch).

I tought that i will be able to capture the full boot process. but the maximum capture size that i got is  223 ms .

I don't undertand in practise what i should do if i want to analyse an unknow board ? set up trigger on CS low ?

Or m i missing something  ? Is this the normal behavior ?

I updated to latest firmware with OLS_Updater too.

Best Regards
Title: Re: capture duration with OLS really short
Post by: sre71 on April 10, 2016, 01:50:11 pm
Hi busowner666,
you are welcome!
Actually the maximum capture size depends on sample rate you are using.
OLS has 216K block RAM that can support different memory configurations depending on how many channels are used:
 
8 channels with 24K sample depth
16 channels with 12K sample depth
32 channels with 6K sample depth
 
Unless RLE is in use the total acquisition time is the fraction of the available sample depth on sampling rate.
So for instance, considering RLE is off, with 8 channels there are 24K sample depth and by sampling at 200MHz it is 24K/200MHz=120us as lasting time for the acquisition.
By using RLE compression the lasting time will be increased.
In this case, regardless by the real number of channels needed for the acquiring, it's better setting the client for all 32 available because it extends the maximum lasting time for the acquisition.
Please take a look at these:
 
viewtopic.php?f=23&t=1711&p=59523&hilit=FPGA+V (http://dangerousprototypes.com/forum/viewtopic.php?f=23&t=1711&p=59523&hilit=FPGA+V)
 
viewtopic.php?f=23&t=1711&p=59523&hilit=FPGA+Verilog+Demon+Core+AdvTrigger+Meta+RLE+Ti#p59523 (http://dangerousprototypes.com/forum/viewtopic.php?f=23&t=1711&p=59523&hilit=FPGA+Verilog+Demon+Core+AdvTrigger+Meta+RLE+Ti#p59523)
 
Good luck!
 
Regards,
sre71
Title: Re: capture duration with OLS really short
Post by: busowner666 on April 10, 2016, 07:52:04 pm
Thanks i understood;

Need some more practise and discipline then with corectly crafted triggers :)
Title: Re: capture duration with OLS really short
Post by: mnbxcv on August 18, 2017, 09:27:25 pm
I'm in the same world of confusion here...  I get that I can create triggers and that the capture buffer is limited to 216K, but I really just want to record everything that happens on the bus (1-wire in my case) for 20 minutes (or more).  My PC has 64GB of RAM, why limit the capture buffer to 216K?

EDIT: Doh! I just realized the 216K buffer is on the OLS, not in the java app running on my PC.  For very slow protocols, like 1-wire, it would be awesome to capture repeatedly since the serial connection to the OLS is significantly faster than the bus being captured.

( ! ) Fatal error: Uncaught exception 'Elk_Exception' with message 'Please try again. If you come back to this error screen, report the error to an administrator.' in /var/www/dangerousprototypes/forum/sources/database/Db-mysql.class.php on line 696
( ! ) Elk_Exception: Please try again. If you come back to this error screen, report the error to an administrator. in /var/www/dangerousprototypes/forum/sources/database/Db-mysql.class.php on line 696
Call Stack
#TimeMemoryFunctionLocation
10.00992060592session_write_close ( )...(null):0
20.01022192184ElkArte\sources\subs\SessionHandler\DatabaseHandler->write( )...(null):0
30.01022192960Database_MySQL->query( ).../DatabaseHandler.php:119
40.05612331696Database_MySQL->error( ).../Db-mysql.class.php:273