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Dangerous Prototypes

Dangerous Prototypes => Bus Blaster JTAG debugger => Topic started by: whoami on June 30, 2015, 07:14:14 pm

Title: BusBlaster v4 SWD Buffer logic
Post by: whoami on June 30, 2015, 07:14:14 pm
Hi,

I got a BusBlaster v4 and I can successfully debug my cortex M3 lpc1768 via JTAG.
Some weeks ago I designed a board and got it now.

The problem is I put a 10 pin header on the board for SWD debug.

Now I am trying to find a buffer logic (like KT-Link) for the BusBlaster v4
Is there any logic available?
I havn't found any for the v4

Best regards
Title: Re: BusBlaster v4 SWD Buffer logic
Post by: natevw on September 24, 2015, 12:07:01 am
Looks like there is a thread about this, reporting some success, here: viewtopic.php?f=37&t=5954 (http://dangerousprototypes.com/forum/viewtopic.php?f=37&t=5954)

(I have not finished trying that myself, yet.)
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#TimeMemoryFunctionLocation
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