Hi there,
Self test shows
0 ERRORS!
Its first time I tried to interface a 5V SPI and it didn't work. So I checked what is going on on oscilloscope.
I open-drain (Hi-Z mode) CS and CLK operate on 0-5V level, but MOSI works just on 0-3,3V and doesn't have similar open-drain signal path.
I added a picture for better understanding. Blue (CH2) is CLK,
yellow (CH1) is MOSI[attachment=0]
Thank you for help, good day
version:Bus Pirate v3.5
Firmware v6.1 r1676 Bootloader v4.4
DEVID:0x0447 REVID:0x3046 (24FJ64GA002 B8)
http://dangerousprototypes.com (http://dangerousprototypes.com)
CFG1:0xFFDF CFG2:0xFF7F
Did you enable pullups (P) and connect 5V to Vpu pin and turn on the power suplies (W)?
Yes, power supplies are ENABLED, VPU is CONNECTED to +5V and pullups are ENABLED.
I open-drain mode I wouldn't get CLK signal (couldn't trigger) if that was not the case.
Can you test it without the device in circuit to see if still MOSI is swinging between 0-3.3V? I'm trying to understand where the problem is. If there was a problem with BP, self-test should've captured it.
I made a test without the device connected (picture included). MOSI is still 0-3.3V.
[attachment=0]
http://http://dangerousprototypes.com/forum/viewtopic.php?f=4&t=4844&hilit=mosi+open+drain ??
I interfaced a chip (MAX7219) directly with a micro now. For further projects would like to use BP. As it's faster for just few SPI commands. Have to sort this out.
Yep, I remember that thread. The thing is, if open-drain transistor was toast, you wouldn't be able to get logic 0 levels which you are getting. One problem I was thinking about was if the chip under test was doing something funny but it's not that. The problem is on the high side and isolated with the MOSI pin only.
Your +5V supply is solid, I can see that from the scope. The other components on that side is the 2k pullup resistor (R5) and 4066 analog switch. Can you update the firmware to v6.2 or v6.3 beta test firmwares and check it all again? There may be a firmware problem, we may not be configuring all pins as open drain (which is quite strange) or it's a hardware problem related to 4066 and/or some problems on the board. For that can you measure the voltage level from 4066 side of R5 (highlighted part in the picture)?
[attachment=0]
I did update the firmware to:
Bus Pirate v3.5
Firmware v6.3-beta1 r2151 Bootloader v4.4
DEVID:0x0447 REVID:0x3046 (24FJ64GA002 B8)
http://dangerousprototypes.com (http://dangerousprototypes.com)
Oscilloscope picture from previous post is also with the v6.2-beta1 r1981 firmware as I updated 2 days ago.
Test shows everything is ok. 0 errors.
On 4066 side of R5, measured voltage is 5V.
It definitely seems like MOSI is PUSH-PULL pin as you get this kind of voltage characteristic. With open-drain you have a noticeable curve because of pull-up.
I couldn't find definition of BP_MISO_ODC register which supposedly controls the open-drain enable, disable? You probably know where it is defined. It should be something like register ODCx: PORTx Open-Drain Control register (PORT B, pin 9) http://http://ww1.microchip.com/downloads/en/DeviceDoc/39711b.pdf
If you have same firmware and cannot reproduce the "bug", it is microcontrollers fault! No other option I think.
Yep, tested on my v2 and I have the same problem.
The problem is on some v3, the pullup resistor is lower than others so it may not look so clear. But you are right, it does not follow the pullup curve.
For register definitions, look up to hardwarev3.h file where all of these stuff are defined. The register definition there is correct.
I tested it out and I can say that I can see a similar thing on my scope. But the uC is not at fault here! Check the same with 3wire protocol, I see that the voltage change is 5V in this protocol, probably the same thing with you too. Something weird going on over there. If you see the same thing with 3wire, I'll open up a ticket and have a look at the cause. I'll have a look today to see if the same problem is there in v4.
Good job questioning validity of SPI open-drain setting.
I don't have MIcrochip gear to debug, should you set breakpoints and look. I find it strange that if you type
command i, it shows it is open-drain.
*----------* Pinstates:
1.(BR) 2.(RD) 3.(OR) 4.(YW) 5.(GN) 6.(BL) 7.(PU) 8.(GR) 9.(WT) 0.(Blk)
GND 3.3V 5.0V ADC VPU AUX CLK MOSI CS MISO
P P P I I I O O O I
GND 3.28V 5.01V 0.00V 5.02V L L L H H
POWER SUPPLIES ON, Pull-up resistors ON,
Open drain outputs (H=Hi-Z, L=GND)
MSB set: MOST sig bit first, Number of bits read/write: 8
a/A/@ controls AUX pin
SPI (spd ckp ske smp csl hiz)=( 1 0 0 0 1 1 )
*----------* Does this read directly from register? Probably the only valid way.
If I set 3WIRE mode
MOSI IS open-drain (look at picture) and at 5V :)
[attachment=0]
In v4, MOSI and CLK are not set to open drain, but CS is. 3 wire mode has no problems again, all is well with 5V pullups.
Checked v2 again. Only MOSI is problematic, CLK and CS are at 5V levels.
I'll look into this problem.
Could this be the bug in the code:
http://https://code.google.com/p/dangerous-prototypes-open-hardware/source/browse/trunk/Bus_Pirate/Firmware/SPI.c
SPI.c line 42
//open drain control registers for OUTPUT pins
#define SPIMOSI_ODC BP_MISO_ODC
#define SPICLK_ODC BP_CLK_ODC
#define SPICS_ODC BP_CS_ODC
Shouldn't it be MOSI??
Yep, that is the problem. I just compiled and exported the new firmware for v3, can you also check it?
I have no idea about the CLK problem in v4 though. I'll just test this code when I have time for to see if it's fixed or not.
Thank you for compiling, so I didn't need to download and install MPLABX.
It works as it should :)
[attachment=0]
I don't have v4, but I can help you find bugs.
[quote author="luftek"]Thank you for compiling, so I didn't need to download and install MPLABX.
It works as it should :)[/quote]
SWEET!!! But I'd say go ahead and install it. I did some mods to the firmware I have (I was developing some stuff for v4), so I kinda use nightly-builds of the firmware for mine. ;)
[quote author="luftek"]I don't have v4, but I can help you find bugs.[/quote]
I'm actually committed to fixing this issue, the problem is these few weeks have been swamped with work. Over the weekend I'll have some time to have a look at the things and push the changes to the SVN.
I understand, awesome that you have a job. Hopefully I will also, in October. Thank you for your help!! Be good, see you around :)
Hi there,
@tayken
I have downloaded your new firmware.
Honestly even before your bug fix, never I have experimented failure using SPI although there was the problem which was described.
However fine that now it's gone.
From that side for what I can understand all seems to be fine with the new release.
I have noticed your firmware is based on 6.3 release, this show the terminal performing "i" (Versioninfo/statusinfo).
Am I pushy asking what is new in there?
Thanks in advance and thank you very, very much for your fix, improvements and over all this, for sharing it!
Kindest regards,
sre71
Hello sre71,
The only difference is that I just fixed the typo luftek found:
[quote author="luftek"]SPI.c line 42
//open drain control registers for OUTPUT pins
#define SPIMOSI_ODC BP_MISO_ODC
#define SPICLK_ODC BP_CLK_ODC
#define SPICS_ODC BP_CS_ODC
Shouldn't it be MOSI??[/quote]
I didn't change anything else at this point. I'll be looking at a few things for v4, then pushing this to SVN so that it can be included in the next firmware version.
Hi tayken,
thanks for reply.
Ok, I get it.
Well done, at least the MOSI problem is out of business now, thank you!
Due the fact somewhere somebody have already proposed solutions I'm trying to get a portable version of MPLABX in order to try to fix some old issues (viewtopic.php?f=4&t=5052&start=15 (http://dangerousprototypes.com/forum/viewtopic.php?f=4&t=5052&start=15)).
Hoping not damage my Bus Pirate though.
Thanks for sharing!
じゃあまたね
sre71
I don't see a compiled version though in Google? Last compiled version is 2102 v6.2 beta 1? Can someone post an updated compiled version with this source code clerical error fix MISO to MOSI.
I see a compiled version was attached in this thread but what version will it display v6.3 beta1 for example? File "spi_fix.hex"
Thanks
Edited a few minutes later:
It is indeed Firmware v6.3-beta1 r2151.
Thanks