Dangerous Prototypes

Other projects => Past projects => CPLD programmable logic => Topic started by: robm on June 01, 2014, 12:04:56 am

Title: XC9572 Development ???
Post by: robm on June 01, 2014, 12:04:56 am
Hi all,
        I am looking for a medium to high gate count CPLD that will work in with 5V TTL.

I want something that is breadboard compatible so I was looking at the XC9572XL development board.

For the life of me I can't work out how to develop (via schematic entry) for this chip. I am using ISE 14.6 for Spartan FPGA but there is no way to select the XC9500 devices.

Can someone help me get off the ground. I have no preference to Xilinx or the ISE in fact I hate the Xilinx ISE!

I was hoping to have more than 72 Macros as well.
Title: Re: XC9572 Development ???
Post by: USBGuru on June 24, 2014, 02:36:19 am
Hi robm,

You should check out the UnoProLogic. It uses an Altera EPM570 CPLD. It is low cost and is 5V compatible. You can find it Tindie, eBay, and Amazon.
Title: Re: XC9572 Development ???
Post by: robm on June 24, 2014, 04:30:08 am
Hi, Thanks for the info.

I managed the select the XC9572 in the xilinx ISE. By choosing VHDL entry first I was then able to choose the correct device. Once a project was created for VHDL entry for the XC9572, I could then create a project for the same device and with schematic entry. I don't why, it seems like a quirk in the ISE.

I was looking at the XC9572 c-mod development board as it can be plugged into the final project. Nice an skinny.

The one you suggested was double row pins so it isn't not going to work in a breadboard. Also going from 72 macros to 500 odd is a bit much.

Thanks for the advice anyway. I may end up using a smaller chip on a breakout board.
Title: Re: XC9572 Development ???
Post by: udif on June 24, 2014, 08:50:16 pm
Don't be fooled by the EPM570. it's not a 72-macrocell vs 570 thing.
For the XC9572, each macrocell  can accept one or more product terms, where each one is a 54-input AND gate. just like other PAL and CPLD devices.
The EPM570 macrocells are more like 4-bit LUTs, so if you have a wide expression, you will quickly see you're wasting many macrocells to implement it.

The EPM570 is more like a tiny FPGA with built-in nonvolatile configuration memory, and no internal memories (AFAIR).
The best way to benchmark such devices is to take a tiny piece of vhdl/verilog code which you fin useful/representative of what yoiu need, try to fit it using the vendor's tools, and checking the final utilization.

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