Dangerous Prototypes

Other projects => Open Bench Logic Sniffer => Topic started by: mkarlsson on September 10, 2013, 01:23:02 am

Title: Demon 3.07 verilog code ported to Pipistrello LX45
Post by: mkarlsson on September 10, 2013, 01:23:02 am
FYI, I have ported the Demon 3.07 code to Pipistrello LX45 FPGA board with the following changes:

1) The sample buffer size is increased by a factor of 8 from 24kB to 192kB
2) The interface is changed to serial (Pipistrello uses a FTDI 2232H High-speed USB chip)
3) The baud rate is increased from 115200 to 921600 to reduce the data upload time
4) The meta data has changed to indicated Pipistello implementation

I believe this is the largest buffer size of any of the "SUMP" implementations.  It runs great with the latest JaWi OLS Java client.

The implementation uses about 22% of the slices and 96 block rams (out of 116 total). 
BTW, removing the advanced triggers reduce the size to about 7% of the slices making it quite possible to have this as an internal logic analyzer in a FPGA project.

More info and links to the complete XISE project and the bit file can be found at the saanlima forums (sight, the link got blocked, I guess you just have to google "pipistrello fpga").

Magnus
Title: Re: Demon 3.07 verilog code ported to Pipistrello LX45
Post by: mkarlsson on September 11, 2013, 09:06:25 am
Screen shots:
Title: Re: Demon 3.07 verilog code ported to Pipistrello LX45
Post by: mkarlsson on September 13, 2013, 05:19:37 pm
Here is a link to information about the project including the complete XISE project for download:
http://saanlima.com/forum/viewtopic.php?f=9&t=8 (http://saanlima.com/forum/viewtopic.php?f=9&t=8)

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