Hi,
The answer to this might be to aim me at a guide to using the logic analyser for I2C, but so far I've not seen anyone mention this message.
I have an ATmega328 as the master to my I2C bus so am sampling at 200kHz, ie double the I2C bus speed, which I read was the way to go. The I2C analysis results have man lines that show BUS-ERROR. Is that normal contention between slaves or indicative of an issue with my board design, or a 3rd option even?
If there's a decent resource for showing how to sniff and interpret I2C traffic for a first-timer I'll be happy to race off and do that reading if you can recommend something.
Thanks
Geoff
I tried to include the exported I2C Analysis results but even when renamed I get the message : "The upload was rejected because the uploaded file was identified as a possible attack vector."
The I2C decoder works correctly if the timing is sufficiently correct. A sample rate of 200kHz is certainly not sufficient. Try using a sample rate of 1MHz or higher. That should give much better results...
Thanks jawi - will give that a crack tonight.
Hi,
At 1Mhz I get no errors, however very little I2C traffic to analyse even when using a trigger and RLE. I'm certain I'm not doing this right - can you point me at a page where I can read on how best to see my I2C traffic?
Thanks again,
Geoff
It depends a bit on what you're exactly trying to achieve. If you're merely interested in the data itself, you can also use, for example, the BusPirate to sniff and dump the data of your I2C-bus. If you want to debug timing issues in your I2C implementation, you could also opt for a logic analyser with more memory, like the Logic Pirate.
Thanks jawi
This is my first PCB with multiple I2C devices on it, so I was really wanting to confirm that they're all co-existing nicely. The project operates on the bench as I expect but it's really just curiosity on my part to see if there are issues that can be improved on. From what you're saying here I won't be able to do that with the Logic Sniffer which is a shame.
I wasn't aware of the Logic Pirate project but will scoop one up when they come live on seeed and get back to this.
Cheers, Geoff
[quote author="stryker"]Thanks jawi
This is my first PCB with multiple I2C devices on it, so I was really wanting to confirm that they're all co-existing nicely. The project operates on the bench as I expect but it's really just curiosity on my part to see if there are issues that can be improved on. From what you're saying here I won't be able to do that with the Logic Sniffer which is a shame.
I wasn't aware of the Logic Pirate project but will scoop one up when they come live on seeed and get back to this.
Cheers, Geoff[/quote]
I suspect that Jawi actually meant this one:
http://dangerousprototypes.com/docs/Log ... c_analyzer (http://dangerousprototypes.com/docs/Logic_Shrimp_logic_analyzer)
That one is good for 256K samples at up to 20 MHz. That's a good bit deeper than the OBLS. At 1 MHz sample rate, you could get some 256ms of trace capture with the logic shrimp.
Not this? http://dangerousprototypes.com/docs/Logic_Pirate (http://dangerousprototypes.com/docs/Logic_Pirate)
[quote author="stryker"]Not this? http://dangerousprototypes.com/docs/Logic_Pirate (http://dangerousprototypes.com/docs/Logic_Pirate)[/quote]
Perhaps he did mean that one. On the other hand, that one doesn't seem to be available for purchase just yet. The Logic_Pirate (honestly where do they get these names?) does have the advantage of 8 channels vs the Logic Shrimp with just 4 channels. The Logic Pirate also does 40 MHz sample rate if you don't mind over-clocking 2x past the sram spec. Neither the extra channels nor the extra speed will help with I2C. Capture depth is the same 256k on both.
Both devices are based on a similar concept with SPI serial ram. The Logic Pirate appears to be a newer design taking advantage of larger ram, allowing a doubling of channels. If the ram chips were cascaded rather than run in parallel, you could get twice the capture depth and if it had a way to do RLE that would be even better. Given the simplistic nature of the design, there just isn't any easy way to add RLE, though cascading could be made to work.