I recently received and assembled a logic shrimp v2b free PCB. As there was not any readily available firmware for it, I decided to write my own based on the existing code from the previous board revision and the DP open source USB stack. I already have working code to read/write from/to the SRAM in any serial mode (SPI, SDI or SQI), for the PWM-based clock generation ranging from 3000Hz to 12MHz, and the timers. However, when writing the code for the interrupt on change-based trigger, I've realized that two of the bidirectional SIO_X lines (those corresponding to channels 3 and 4) have been linked to non-PPS pins, and thus, it is not possible to use the interrupt on change functionality on them! This revision of the logic analyzer is then limited to edge-triggering on channels 1 and 2 only.
This bug can be easily solved by re-routing the SRAM SIO pins to the RB0-RB3 pins which are indeed remappable pins instead of to the pins they are currently connected to (i.e. RA0-RA3). I believe that this can be easily fixed in a new board revision. I would also recommend adding a tristate buffer between the ext_clock header and the SCLK line to facilitate switching between the OSC_CLK and the clock signal fed through the EXT_CLK header. The output enable pin for this buffer could be connected to any unused pin (e.g. RA0, RA1, RA2, RA3, etc.). This latter mod is not really necessary, but I think it would contribute to a more robust hardware.
Thanks for the detailed debug! I think originally we were using B0-3 in the v1, we're working on an update now. We'll add a footprint for the external tristate buffer too. Be sure and hit me up for the updated board if you notice it on the blog.
it is not possible to use the interrupt on change functionality on them! This revision of the logic analyzer is then limited to edge-triggering on channels 1 and 2 only.