Is the RLE compression implemented inside the FPGA? If so, how are literal samples distinguished from repeats? The FPGA has 18-bit memory, which I suppose could be 16-bit with 2-bit parity, but could one of those extra bits be used as a flag to indicate a literal 16-bit sample vs. an RLE repeat/delay?
it is very simple.. FPGA memory is organized as 32bit memory. If you enable RLE, the bit number 32 is used as "flag", that distinguishes between count and sample.
the code can be interpreted as:
if sample == old_sample:
count = count + 1;
else:
write(count);
write(sample);
count = 0;
old_sample = sample;
This is of course done in parallel style. And has small disadvantage. You loose one bit on the way. And if you use "bitstream" other than 4kx32[in|out]side the RLE is completely broken.
I am not sure about the organization of the memory. (BTW the idea of using parity has been proposed by jack somewhere in the recent threads)
Ok, I thought the OLS was a true 32-channel analyzer, at least when using the Butterfly wing. This makes it seem like one of the wing pins won't get sampled because the RLE flag overwrites it in memory.
I suppose if it is something you can optionally enable, then wing users can disable it if needed.
of course, there is a option to disable RLE
I think that going forward we should probably move the RLE bit into parity and reclaim that 32nd channel. In the case of using external SRAM memory we can have the RLE use internal BRAM.
Jack.