Dangerous Prototypes

Dangerous Prototypes => Bus Blaster JTAG debugger => Topic started by: ian on January 20, 2012, 02:13:46 pm

Title: Bus Blaster v4 power up test success, bitstream next
Post by: ian on January 20, 2012, 02:13:46 pm
There are a number of Bus Blaster v4 free PCBs out there. Anyone build one? I finished the v4 and did the power up test, it enumerated ok. Next to adapt the bitstream and try the self-test.
Title: Re: Bus Blaster v4 power up test success, bitstream next
Post by: robots on January 20, 2012, 07:48:14 pm
nice :) does it work yet ?
Title: Re: Bus Blaster v4 power up test success, bitstream next
Post by: fcobcn on February 05, 2012, 09:55:44 pm
[quote author="ian"]Anyone build one?[/quote]

I'm looking for the CPLD to finish mine.
The wiki partlist says XC2C64A but doesn't seem to be the correct part number.
It will be a nice mate to my recently finished Cygni board.
Title: Re: Bus Blaster v4 power up test success, bitstream next
Post by: ian on February 06, 2012, 08:53:35 am
Exact part number is:    XC2C64A-7VQG100C
Title: Re: Bus Blaster v4 power up test success, bitstream next
Post by: fcobcn on February 06, 2012, 04:02:05 pm
[quote author="ian"]Exact part number is:    XC2C64A-7VQG100C[/quote]

Thanks Ian,
Neither farnell, mouser or rs components carry them.
Do you have any recommendation where to get them in Europe?
Title: Re: Bus Blaster v4 power up test success, bitstream next
Post by: ian on February 06, 2012, 07:58:37 pm
I'm sorry, I don't I got them from digikey. If I had not used both of them makeing prototypes I would send you one.
Title: Re: Bus Blaster v4 power up test success, bitstream next
Post by: fcobcn on February 06, 2012, 08:07:25 pm
No worries,
I will wait until I have more digikey only available products and will do a batch order (have a couple more already).
Title: Re: Bus Blaster v4 power up test success, bitstream next
Post by: Ice9er on February 09, 2012, 04:32:40 am
Hello everyone.  New to the form.  First post :)
I'd love to put one of these V4s together and try to get it working.  Do you have any PCBs left?  If so, let me know how I can get a hold of one.  If not, when do you think you will get another batch?  Find any artwork bugs that need a new cut?
Thanks.
NLC
Title: Re: Bus Blaster v4 power up test success, bitstream next
Post by: ian on February 09, 2012, 02:17:05 pm
I'm sorry NLC, this one was super popular and  all the PCBs are gone. There is a chance of another batch, depending on if there are bugs in this version, otherwise it will go straight to production.
Title: Re: Bus Blaster v4 power up test success, bitstream next
Post by: robots on February 09, 2012, 04:36:26 pm
Can't wait for the next batch ..... :-)

Anyway, how are the tests coming ?
Title: Re: Bus Blaster v4 power up test success, bitstream next
Post by: Ice9er on February 16, 2012, 04:33:19 am
How's the debug progress going?  I know you probably hate this question by now, but could you take a rough guess as to when you think more boards or a finished unit would be available?  Weeks, months, years?
Title: Re: Bus Blaster v4 power up test success, bitstream next
Post by: ian on February 16, 2012, 07:06:14 am
Probably years, this is just a fun project, we have no intent to produce it at all at this time.
Title: Re: Bus Blaster v4 power up test success, bitstream next
Post by: ian on March 02, 2012, 02:48:05 pm
Quote
Hi, I received your board and I want to buy components but I don't known reference of FTDI chip if it's ft2232hl or ft4232hl

 I don't find any value of inductors in ft2232's datasheet. What are values that you put ?
Can I use xc2c256-vq100 for cpld ?

Thanks

Bus Blaster v4 uses ft2232H.

Any ferrite bead will work, or just leave it off and solder a jumper. Here's our beads:
http://dangerousprototypes.com/docs/Par ... rrite_Bead (http://dangerousprototypes.com/docs/Partlist#Ferrite_Bead)

That CPLD is fine. More expensive and you will need to compile your own bitstreams.
Title: Re: Bus Blaster v4 power up test success, bitstream next
Post by: iens on March 17, 2012, 09:39:03 am
Hello, I finnished to sold component on the board, but I can't programme cpld. I notice that 1.8V power pins of CPLD isn't powered by ftdi, the 1.8v track isn't routed with the pin regout of ftdi. Is it an error or not ?
Title: Re: Bus Blaster v4 power up test success, bitstream next
Post by: ian on March 26, 2012, 07:50:21 pm
You are totally right. The net is named +5V and is not connected. You will need to solder a jumper from C19 or C23 to C1, C2, C3, or C8.
Title: Re: Bus Blaster v4 power up test success, bitstream next
Post by: skot9000 on April 11, 2012, 03:16:51 am
Hello,

I got a Bus Blaster v4 from the Free PCB drawer. I have soldered it together, and I *think* I have successfully programmed the CPLD.

I wasn't able to find a BBv4 bitstream, so I edited the jtagkey buffer ucf file to match the new XC2C64A VQ100 pinout and generated a new SVF file.

I installed UrJTAG 0.10 #2024 from SVN and was able to get it to compile on OS X using
Code: [Select]
./autogen.sh --disable-werror
Next I googled around for a XC2C64a bsdl file; http://http://bsdl.info/view.htm?sid=bf5910466c75c02088ca59b002289d77

and followed the instructions on the http://http://dangerousprototypes.com/docs/Bus_Blaster_v2_manufacturing_resources

The next step seems to be getting the self test to work.
Title: Re: Bus Blaster v4 power up test success, bitstream next
Post by: skot9000 on April 11, 2012, 04:59:31 am
Is there an ISE project for the BBv4 Self test buffer?

With my modified version of the BBv2 jtagkey buffer, UrJTAG does recognize both CPLDs on my old Digilent XC2-XL dev board.

Code: [Select]
jtag> cable jtagkey interface=0
Connected to libftd2xx driver.
jtag> detect
IR length: 16
Chain length: 2
Device Id: 01001001011000000100000010010011 (0x49604093)
  Manufacturer: Xilinx (0x093)
  Part(0):      xc9572xl (0x9604)
  Stepping:    4
  Filename:    /usr/local/share/urjtag/xilinx/xc9572xl/xc9572xl_cs48
Device Id: 00000110110101001100000010010011 (0x06D4C093)
  Manufacturer: Xilinx (0x093)
  Part(1):      XC2C256-TQ144 (0x6D4C)
  Stepping:    0
  Filename:    /usr/local/share/urjtag/xilinx/xc2c256-tq144/xc2c256-tq144
Title: Re: Bus Blaster v4 power up test success, bitstream next
Post by: ian on April 17, 2012, 05:44:27 pm
Hi skoot9000,

Fantastic news, thank you for sharing. Would you be willing to contribute the modified .ucf file for BBv4?

As far as I know there is no bitstream project at all for BBv4 yet, I had planned to do the self test buffer first because it's the one we use in manufacturing.
Title: Re: Bus Blaster v4 power up test success, bitstream next
Post by: skot9000 on April 18, 2012, 01:00:33 am
Sure.

I haven't done a lot of testing with it, but UrJtag seems to recognize connected CPLDs fine.
I couldn't figure out what to do with "TARGET_PRESENT" input so I hardcoded the "FT_TARGET_PRESENT" output to 0 in the verilog.

here is my UCF file and the SVF file I generated.
[attachment=0]

I guess I meant; Is there a BBv2 Self-test ISE project I can look at to modify into one for BBv4?
Title: Re: Bus Blaster v4 power up test success, bitstream next
Post by: ian on May 30, 2012, 04:29:23 pm
Hey Skot,

Thanks for the UCF. The self-test buffer wasn't actually in SVN for some reason, so I checked it in at the beginning of the month with an updated ucf for the v3 Bus Blaster. I'm sorry,It looks like I forgot to reply here.

Here's the self-test jtagkey buffer with ISE projects for v2 and v3:
http://code.google.com/p/dangerous-prot ... AGkey_test (http://code.google.com/p/dangerous-prototypes-open-hardware/source/browse/#svn%2Ftrunk%2FBus_Blaster%2Fbuffer_logic%2FJTAGkey_test)

I'm going take a look at what needs to be added to the v4 UCF to get it going with the self-test buffer.
Title: Re: Bus Blaster v4 power up test success, bitstream next
Post by: ian on May 30, 2012, 04:55:10 pm
It looks like we removed target_present from v4. Wiring either way is probably ok, I don't think many programs rely on it.

I added your ucf to the test mode buffer folder in SVN. I made a few tiny changes:

Code: [Select]
NET "FT_DBGACK"         BUFG = CLK;  #AC5 is clock out in 485 mode

because FTDBGACK is clock out for a potential 60MSPS logic analyzer mode and we did make the effort to route it to a GSK pin :)
Code: [Select]
//control pins for test mode
input wire TEST_MODE_0; //has pullup, pull low to ground to enter test mode
inout wire TEST_MODE_1; //outputs high (light LED) on test mode active
wire TEST_MODE;

There are 2 new signals and pins used by the test buffer, Test_MODE_0 and TEST_MODE_1. There is a TEST_MODE_2 too, but it is unused and should be removed (I may check in one with it removed now).

Code: [Select]
#trigger pins for test mode
NET "TEST_MODE_0"    LOC =  "P1"; #test mode trigger pin, pull low to enter test mode
NET "TEST_MODE_0"    PULLUP;
NET "TEST_MODE_1"    LOC =  "P64"; #test mode output pin, usually the LED
NET "TEST_MODE_1"    PULLUP;

I added them to the v4 UCF and assigned the trigger pin to P1, short it to ground to enter test mode. (Make sure the on-board power jumper JP4 is closed to power the front end with 3.3volt from the on-board regulator). Output is on P64 through the indicator LED.

Latest SVN is attached as a zip, though I have not had a chance to synthesize and test it yet.

Please note that this does not test the additional connections on the secondary JTAG bus of the FT2232. That will need updated buffer, as well as a new test application.
Title: Re: Bus Blaster v4 power up test success, bitstream next
Post by: skot9000 on June 12, 2012, 03:49:04 am
I'm not really sure how the self-test works, but it looks like something is two bits off... here is the output I get from the self-test .bat file;

Code: [Select]
C:Documents and SettingsAdministratorDesktopbusblasterdangerous-prototypes
manufacturing_resourcesv2-selftest>BusPiratev2Test_VisualC++Express.exe -delay
-n0
Select device:
Device 0 (Serial Number: FTVDJFA1A

======================================================
SUCCESS (Connected to the FTDI.FTVDJFA1A)
SUCCESS (reset)
SUCCESS (usb parameters set)
SUCCESS (event chars disabled)
SUCCESS (timeouts set)
SUCCESS (latency set)
SUCCESS (flow control disabled)
SUCCESS (MSSPE reset)
SUCCESS (MPSSE on)
START TESTING

======================================================
        00000001        11000001
        00000010        11000010
        00000100        11000100
        00001000        11001000
        00010000        11010000
        00100000        11100000
        01000000        11000000
        10000000        11000000
        00000000        11000000
        10101010        11101010
        01010101        11010101
        00000000        11000000
        11111111        11111111
Testing complete, errors: 12

C:Documents and SettingsAdministratorDesktopbusblasterdangerous-prototypes
manufacturing_resourcesv2-selftest>pause
Press any key to continue . . .
Title: Re: Bus Blaster v4 power up test success, bitstream next
Post by: ian on June 12, 2012, 12:46:14 pm
Hey Skot,

Thanks for the test and update. The self test puts patterns on the FT2232's 8 ADbus pins. THe buffer loops them through the JTAG header and back to the FT2232's 8 ACbus pins. The value shown is the returned byte from the ACbus.

I am guessing the upper two bits are AC/ADbus 6 and 7

Code: [Select]
NET "FT_RTCK"        LOC =  "P49";   #AD7
NET "FT_nSRST_IN"    LOC =  "P50";  #AD6
#unused ft2232 connections
#NET "ACBUS6"      LOC =  "P40";
#NET "ACBUS7"      LOC =  "P39";

Hum - on my copy of the v4 UCF C6 and 7 are commented out. Did you fix that before synthesizing? Maybe they were randomly assigned. That could be the problem. I updated the version in SVN.

If that is not the issues, could you please run the test without the jumpers on the JTAG header, that will help determine if the problem is before or after the buffer.
Title: Re: Bus Blaster v4 power up test success, bitstream next
Post by: skot9000 on June 12, 2012, 10:27:54 pm
Ah ha! That's prolly my fault — not sure why I commented those out. anyways, the tests pass with the following;

Code: [Select]
#unused ft2232 connections
NET "ACBUS6"      LOC =  "P37";  #AC6
NET "ACBUS7"      LOC =  "P36";  #AC7

self-test output;
Code: [Select]

C:Documents and SettingsAdministratorDesktopbusblasterdangerous-prototypes
manufacturing_resourcesv2-selftest>BusPiratev2Test_VisualC++Express.exe -delay
-n0
Select device:
Device 0 (Serial Number: FTVDJFA1A

======================================================
SUCCESS (Connected to the FTDI.FTVDJFA1A)
SUCCESS (reset)
SUCCESS (usb parameters set)
SUCCESS (event chars disabled)
SUCCESS (timeouts set)
SUCCESS (latency set)
SUCCESS (flow control disabled)
SUCCESS (MSSPE reset)
SUCCESS (MPSSE on)
START TESTING

======================================================
        00000001        00000001
        00000010        00000010
        00000100        00000100
        00001000        00001000
        00010000        00010000
        00100000        00100000
        01000000        01000000
        10000000        10000000
        00000000        00000000
        10101010        10101010
        01010101        01010101
        00000000        00000000
        11111111        11111111
Testing complete, errors: 0

C:Documents and SettingsAdministratorDesktopbusblasterdangerous-prototypes
manufacturing_resourcesv2-selftest>pause
Press any key to continue . . .
Title: Re: Bus Blaster v4 power up test success, bitstream next
Post by: ian on June 13, 2012, 09:33:05 am
Yeah! Thanks for the followup. I need to build the a revision with the fixed 1.8volt rail, then I think this is ready for a small initial batch.
Title: Re: Bus Blaster v4 power up test success, bitstream next
Post by: kneegro3 on June 23, 2012, 11:16:17 am
Glad to hear it, i'll be looking forward to it!!! I'd love to bulld one
Title: Re: Bus Blaster v4 power up test success, bitstream next
Post by: mikelelere on September 04, 2012, 01:48:11 pm
I've recently built the Bus Blaster v4 board shown in the photograph. It cannot be seen properly in the image, but for this build I used a Xilinx XC2C128-VQ100 instead of the XC2C64A used in the original design. Note also the ugly patch I had to perform to power the CPLD and FT2232H cores using an external 1.8v voltage regulator (as can be seen in the image, the FT2232H internal regulator cannot be accessed due to a missing pin).

I checked the board via the test program, and it successfully passed the tests (see the attached photographs). I've also succesfully used it to program a Coolrunner II CPLD board and a Lattice ISPMach128v CPLD, and I can confirm that the board is working flawlessly.

I'm sharing the compiled buffer for the XC2C128 (the svf file + the complete ISE project) just in case anyone is interested. I did not perform any modifications on the code provided by Skot for the  XC2C64A-VQ100, since it was not necessary.

Regards,

M.
Title: Re: Bus Blaster v4 power up test success, bitstream next
Post by: Grapsus on September 06, 2012, 09:36:06 am
Hi there !

I was wondering if you have any BBv4 PCB left (I have a free PCB code) ? I'd really like to build one and test it. Moreover I have access to the exact right CPLD part (XC2C64A-7VQG44C available on french Farnell with free shipping).

Thanks !
Title: Re: Bus Blaster v4 power up test success, bitstream next
Post by: ian on September 10, 2012, 04:02:09 pm
mikelelere - thanks for verifying the design and reporting results. I think I forgot to submit my reply last week, but I did get it onto the blog  :)

Grapsus - I will put the final v4.1 design with standard PCB footprint in the store shortly. To get it early pls email or PM me your code and address and I'll send it out today.
Title: Re: Bus Blaster v4 power up test success, bitstream next
Post by: Grapsus on October 02, 2012, 01:07:44 am
Hi there !

@Ian I got the PCB last friday, thank you very much !

I got the components I didn't have already this morning from Farnell. I had to take the 128 cells CPLD version as the 64 one was sold out. A photo of my build is attached.

Man, this VQFP100 CPLD chip was such a pain to solder !
I didn't populate the I2C EEPROM yet, I will do it later to customize the VID/PID if everything else works fine.

My board powered up OK, the FT2232 was recognized. Then I spent two hours building urJTAG with libftd2xx. Finally the CPLD is alive :

Code: [Select]
warning: UrJTAG may damage your hardware!
Type "quit" to exit, "help" for help.

jtag> cable ft2232 interface=0
Connected to libftd2xx driver.
jtag> detect
warning: TDO seems to be stuck at 1
jtag> cable ft2232 interface=1
Connected to libftd2xx driver.
jtag> detect
IR length: 8
Chain length: 1
Device Id: 00010110110110001010000010010011 (0x16D8A093)
  Manufacturer: Xilinx (0x093)
  Unknown part! (0110110110001010) (/usr/local/share/urjtag/xilinx/PARTS)

I will try to flash the JTAGKey image tomorrow.
Title: Re: Bus Blaster v4 power up test success, bitstream next
Post by: Grapsus on October 02, 2012, 10:57:35 am
Code: [Select]
C:UsersGrapsusDesktop>BusPiratev2Test_VisualC++Express.exe -delay -n0
Select device:
Device 0 (Serial Number: A
Device 1 (Serial Number: B

======================================================
SUCCESS (Connected to the FTDI.A)
SUCCESS (reset)
SUCCESS (usb parameters set)
SUCCESS (event chars disabled)
SUCCESS (timeouts set)
SUCCESS (latency set)
SUCCESS (flow control disabled)
SUCCESS (MSSPE reset)
SUCCESS (MPSSE on)
START TESTING

======================================================
        00000001        00000001
        00000010        00000010
        00000100        00000100
        00001000        00001000
        00010000        00010000
        00100000        00100000
        01000000        01000000
        10000000        10000000
        00000000        00000000
        10101010        10101010
        01010101        01010101
        00000000        00000000
        11111111        11111111
Testing complete, errors: 0

I confirm that my Bus Blaster v4.1 is up and running without any patch wire.

I'm kind of ashamed : at first the test was giving 4 errors suggesting a short between TRST and DBGRQ and indeed I left a small blob of solder between two legs of RN3 which is so easy to solder compared to the CPLD.

@mikelelere thank you for sharing the SVF for XC2C128 test image !
Title: Re: Bus Blaster v4 power up test success, bitstream next
Post by: Grapsus on October 02, 2012, 11:36:01 am
Here is a better picture after a good IPA cleaning, in case you want to post it on your blog.
Title: Re: Bus Blaster v4 power up test success, bitstream next
Post by: Grapsus on October 03, 2012, 11:57:30 am
I soldered an I2C EEPROM and customized the VID/PID data with the utility from FTDI :

Code: [Select]
[  113.023463] usb 2-1.1: new high-speed USB device number 4 using ehci_hcd
[  113.120867] usb 2-1.1: New USB device found, idVendor=0403, idProduct=8879
[  113.120879] usb 2-1.1: New USB device strings: Mfr=1, Product=2, SerialNumber=3
[  113.120887] usb 2-1.1: Product: Bus Blaster
[  113.120893] usb 2-1.1: Manufacturer: Dangerous Prototypes
[  113.120899] usb 2-1.1: SerialNumber: 4.1

As expected the device stopped being recognized by Windows, so I had to create an inf file and install it manually, which is kind of painful. Hopefully I don't use Windows much.
For Linux there seems to be a big drawback : urJTAG doesn't recognize the chip anymore, even with "cable ft2232 vid=... pid=...".
The solution I found is to provide a file named "libft2dxx_table.so" which tells the FTDI driver to take your custom PID into account. It can build using this source :
http://svn.icmb.utexas.edu/svn/reposito ... lib_table/ (http://svn.icmb.utexas.edu/svn/repository/trunk/zpub/sdkpub/usbkey_dlpd/linux/d2xx/lib_table/)

It will be pretty annoying to do that on every computer on which I will use my bus blaster, so I'm not sure if I will keep the custom PID.

@Ian please could you please release the source code of the test utility ? I'd like to study it and port it to Linux, which shouldn't be too complicated.
Title: Re: Bus Blaster v4 power up test success, bitstream next
Post by: ian on October 12, 2012, 03:58:43 pm
Thanks for the tests, pictures, and posts.

The code for the utility is in SVN here:
http://code.google.com/p/dangerous-prot ... 253Dclosed (http://code.google.com/p/dangerous-prototypes-open-hardware/source/browse/#svn%2Ftrunk%2FBus_Blaster%2Fsoftware%2FBBv2-selftest%253Fstate%253Dclosed)

I think it will actually be easier to run the test under linux, on windows the compiling with divers is a pain to get setup.
Title: Re: Bus Blaster v4 power up test success, bitstream next
Post by: Grapsus on October 13, 2012, 01:10:12 pm
Here is a patch so that the test utility builds both on Linux and Windows :
Code: [Select]
Index: main.cpp
===================================================================
--- main.cpp (revision 2034)
+++ main.cpp (working copy)
@@ -11,14 +11,23 @@
  *
  */
 
+#ifdef _WIN32
 #include <Windows.h>
 #include <WinDef.h>
+#else
+#include <inttypes.h>
+typedef uint32_t DWORD;
+#endif
 #include <stdio.h>
 #include <stdlib.h>
 #include <malloc.h>
 #include <time.h>
 
+#ifdef _WIN32
 #include "ftdi/ftd2xx.h"
+#else
+#include <ftd2xx.h>
+#endif
 
 #define MAX_DEVICES 10
 
@@ -37,17 +46,16 @@
 FT_STATUS    ftStatus;
 int          shortDelay;
 
-
+#ifdef _WIN32
 struct timespec {
-  int tv_sec;        /* seconds */
-  long  tv_nsec;      /* nanoseconds */
+  int tv_sec;        /* seconds */
+  long  tv_nsec;        /* nanoseconds */
 };
+#endif
 
-
 struct timespec T;
 
-
-
+#ifdef _WIN32
 void nanosleep(struct timespec *x, struct timespec *y){
  if (shortDelay){
    Sleep(10);
@@ -55,6 +63,7 @@
        Sleep(1000*x->tv_sec+x->tv_nsec/100000000);
  }
 }
+#endif
 
 unsigned char kbhit_getc()
 {
Index: Makefile
===================================================================
--- Makefile (revision 0)
+++ Makefile (working copy)
@@ -0,0 +1,7 @@
+all: BusPiratev2Test
+
+BusPiratev2Test: main.o
+ gcc -o $@ $< -lftd2xx
+
+clean:
+ rm -f *.o BusPiratev2Test

Assuming you installed ftd2xx.h and libftd2xx.so to /usr or /usr/local, just use make to build.

Code: [Select]
$ make
g++    -c -o main.o main.cpp
gcc -o BusPiratev2Test main.o -lftd2xx
$ sudo ./BusPiratev2Test -n0
Select device:
Device 0 (Serial Number: 4.1A
Device 1 (Serial Number: 4.1B

======================================================
SUCCESS (Connected to the FTDI.4.1A)
SUCCESS (reset)
SUCCESS (usb parameters set)
SUCCESS (event chars disabled)
SUCCESS (timeouts set)
SUCCESS (latency set)
SUCCESS (flow control disabled)
SUCCESS (MSSPE reset)
SUCCESS (MPSSE on)
START TESTING

======================================================
00000001 00000001
00000010 00000010
00000100 00000100
00001000 00001000
00010000 00010000
00100000 00100000
01000000 01000000
10000000 10000000
00000000 00000000
10101010 10101010
01010101 01010101
00000000 00000000
11111111 11111111
Testing complete, errors: 0
Title: Re: Bus Blaster v4 power up test success, bitstream next
Post by: systemstech on November 07, 2012, 04:56:21 pm
Thanks to skot9000 and the "Bus Blaster v2 manufacturing resources" post I was able to setup my BBv4.1a.
(http://http://farm9.staticflickr.com/8348/8164206512_b38f2944e1.jpg) (http://http://www.flickr.com/photos/79192364@N07/8164206512/)
IMG_4533 (http://http://www.flickr.com/photos/79192364@N07/8164206512/) by systems tech (http://http://www.flickr.com/people/79192364@N07/), on Flickr

Code: [Select]
UrJTAG 0.10 #1869
Copyright (C) 2002, 2003 ETC s.r.o.
Copyright (C) 2007, 2008, 2009 Kolja Waschk and the respective authors

UrJTAG is free software, covered by the GNU General Public License, and you are
welcome to change it and/or distribute copies of it under certain conditions.
There is absolutely no warranty for UrJTAG.

jtag.c:518 main() Warning: UrJTAG may damage your hardware!
Type "quit" to exit, "help" for help.

jtag> cable ft2232 interface=1
Connected to libftd2xx driver.
jtag> bsdl path c:/bsdl
jtag>
jtag> detect
IR length: 8
Chain length: 1
Device Id: 00000110111001011100000010010011 (0x06E5C093)
  Filename:    c:/bsdl/XC2C64A.bsd
jtag> svf c:/svf/bbv4.svf progress stop
Parsing  1210/1217 ( 99%)
Scanned device output matched expected TDO values.
jtag>

Now to try to do the self test.
Title: Re: Bus Blaster v4 power up test success, bitstream next
Post by: Ice9er on January 05, 2013, 12:20:15 pm
What were the changes between v4, v4.1 and v4.1a?  Was the only hardware issue the 1.8V fix and a re-layout to the standard PCB size, or did other things change?  Are there any other modifications that need to be done to bring a V4 board up to V4.1a functionality wise?  I built up a V4 with the 1.8V mod wire back in the day, but didn't test it any further than plugging it in and talking to the FTDI chip.
Title: Re: Bus Blaster v4 power up test success, bitstream next
Post by: ian on January 09, 2013, 11:25:49 am
**Was the only hardware issue the 1.8V fix and a re-layout to the standard PCB size, or did other things change?

That's it, v4.1 should otherwise be fine.
Title: Re: Bus Blaster v4 power up test success, bitstream next
Post by: Bingo on January 31, 2013, 08:25:42 pm
Is there an expected timeframe for the BBv4 to hit resale in EU ?

I'm looking for a BB , but it seems like only v2' are on sale , did v3 ever hit the market ?

Ohh.. And is BBv4 as "usable" as the v2 , i mean is the firmware done ?

I will be able to do reprogramming on the CPLD (have a Xilinx Jtag) , and a BusPirate.
But i'm a noob on VHDL and/or Verilog yet ....

So i can only program a ready made bitstream.

/Bingo
Title: Re: Bus Blaster v4 power up test success, bitstream next
Post by: ian on February 01, 2013, 06:05:23 am
>>Is there an expected timeframe for the BBv4 to hit resale in EU ?

Depends if anyone wants to carry it :) We haven't even started manufacturing so it could be a while.

>>I'm looking for a BB , but it seems like only v2' are on sale , did v3 ever hit the market ?

v3 is just v2 with a new shape, also not manufactured yet.

>>Ohh.. And is BBv4 as "usable" as the v2 , i mean is the firmware done ?

Yes, v4 is "done" and no further updates are needed (assuming there's no hardware bugs that crop up later). It is just an update of v2/3 with the "you will never even find a chip that uses it" feature of the new SWD reduced wire debugging protocol.

>>I will be able to do reprogramming on the CPLD (have a Xilinx Jtag) , and a BusPirate.
But i'm a noob on VHDL and/or Verilog yet ....

BB is usb upgradable, so no programmer needed :)
Title: Re: Bus Blaster v4 power up test success, bitstream next
Post by: danielgrant007 on July 25, 2020, 03:36:40 pm
Bus Blaster v4 is an experimental, high-speed JTAG debugger from Dangerous Prototypes.

Thanks to a reprogrammable buffer, a simple update over USB makes Bus Blaster compatible with many different JTAG debugger types in the most popular open source software.

Based on FT2232H with high-speed USB 2.0

Buffered interface works with 3.3volt to 1.8volt targets

Reprogrammable buffer is compatible with multiple debugger types

Compatible with 'jtagkey', 'KT-link' programmer settings in OpenOCD, urJTAG, and more

ships with JTAGkey compatible buffer image pre-programmed

Should support Serial Wire Debug when available

Mini-CPLD development board: self programmable, extra CPLD pins to header

Open source (CC-BY-SA)

Bus Blaster Manual

Bus Blaster design overview

Bus Blaster forum

CPLD buffer logic overview

V4 uses a larger CPLD than previous versions. It can now support the SWV feature of Cortex microcontroller for advance debugging when software support is available

ŸSWV is little used and not currently supported in software, most users will be better off with Bus Blaster v3 available here

Fitted in a DP9056 (90x56 mm) standard PCB

Added series resistors to input and output pins to protect against damage and noise

Updates in v4:

Each unit is tested before it ships.

This open source hardware and software is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.