Post away :)
niiiiiiiiice
Sorry for the necromancy. Are these boards being offered for sale? I saw the 64 macrocell board, which is lovely, but a Coolrunner with 128 or more macrocells would be lovlier.
A bit off-topic for this thread, but I have to ask anyways....
I've got to experience whatsoever with CPLDs nor FPGAs so for me 64/128 macrocells sounds like a very small number (unless of course a macrocell is a very powerful unit). How much/what can you actually do with a device like this? Anything fairly complex or just replace a few 74xx glue chips in a design?
With "fairly complex" I mean like receiving a high speed SPI stream and pushing out every other 4 bytes onto four"parallel ports" toggling a byte-received pin and also handle frame synchronization?
Take a look at our wiki. I t has some example whihc should compile and are easily understandable. After you compile a design you get a report that tells how many resources are used. You could also start a new project based on your needs and compile it to see if it fits.
definitiion of macrocell (the description applies more to asic, but the interconnection are programmable in cpld) is here: http://en.wikipedia.org/wiki/Macrocell_array (http://en.wikipedia.org/wiki/Macrocell_array)
Ok thanks. It seems like it's time to start playing a bit with programmable logics... I'll get one of the boards at my next Seeed order.
Is the DSJTAG they also sell any good using Win7/64 - or should I get another JTAG device? BusBlaster?
[quote author="matseng"]A bit off-topic for this thread, but I have to ask anyways....
I've got to experience whatsoever with CPLDs nor FPGAs so for me 64/128 macrocells sounds like a very small number (unless of course a macrocell is a very powerful unit). How much/what can you actually do with a device like this? Anything fairly complex or just replace a few 74xx glue chips in a design?
With "fairly complex" I mean like receiving a high speed SPI stream and pushing out every other 4 bytes onto four"parallel ports" toggling a byte-received pin and also handle frame synchronization?[/quote]
Most of the time they are used for replacing glue ICs (74xx and 4xxx series), helping with the routing and level conversion. You cannot do crazy stuff with them but they do the job if you don't expect too much.
Your "fairly complex" idea may be possible. But cannot be sure, VHDL and Verilog is a hard thing to master and there are lots of factors there. Maybe with a 128 macrocell one you can do it?
[quote author="matseng"]Ok thanks. It seems like it's time to start playing a bit with programmable logics... I'll get one of the boards at my next Seeed order.
Is the DSJTAG they also sell any good using Win7/64 - or should I get another JTAG device? BusBlaster?[/quote]
I only used BusBlaster with urJtag on my Linux system but as I know it works with Windows too. For starters you can use Bus Pirate if you don't want to invest on a special adapter now, it takes a while (okay, sometimes more than a while) to load the bitstreams but it works.
I think it won't fit into 64 cells, but should work with 128. What you basically need is a 32bit shift register (serial in, parallel out) followed by a 32bit latch (so state won't change when receiving data). This needs 64 cells. Then you would need a 5bit-counter (for frame sync) and maybe some glue logic. So you end up with about 70-something cells, I think.
As an example what you can do with 64 cells, look at http://http://blog.hendriklipka.de/archives/2012/07/freqcounter_cpld2.html. This is an example for a frequency counter which has constant precision (so it measures even 1Hz signals with about 1ppm resolution). This is something which needs about 16 or 17 discrete 74xx chips, maybe even more.
My current project is a device to emulate electronically the mechanical 'quick change gear box' common on many lathes.
The design includes an 8x8 grid of 11 bit values, pretty much like an rom. There are 16 address lines, half for the rows, half for the columns (there was no benefit to MUXing them.) An encoder on the lathe's spindle produces a series of pulses which are counted by (of all things) a counter. If the value of the counter matches the value produced by the 'rom', a pulse is sent to a stepper motor. In addition, some of the 8x8 'rom' settings require special lathe setups, so there are 4 enunciators plus a fault signal. Finally, since I have to reverse the lathe in order to cut metric threads, the counter is sensitive to the direction and counts backwards when the spindle us running backwards.
I tell you this because the design seems fully functional and fits into 68 macrocells. That's a small 8x8x11 rom-like structure, an 11-bit up-down counter, and a similarly wide comparator that produces a cam-like effect. I'll have to work a little harder to get it to fit into a 64 macrocell Coolrunner. I am a beginner so this should not be difficult.
I am going to write-up and post this project a bit later, possibly for the logic competition since CPLD designs are allowed there.
It's whatever the judges like. If it is in the spirit of the competition and is educational about logic, then I'm sure they'll evaluate it on the merits.