Dangerous Prototypes

Hi,

as everybody else I've had issues with floating input channels picking up noise or signals from adjacent channels. Grounding unused channels does the trick, but these probes like to slip and it can get a bad mess of wires ;-)

To solve this problem (for me at least) permanently I made a little board:

It supports selectable pull-up and pull-down resistors in two groups with selectable pull-up voltage (2.5V, 3.3V, 5.0V). The pull-down resistors are 10k, which seems to work reliably so far. The size of the pull-up resistors that work reliably depends on the selected voltage. 5.0V and 3.3V works OK with 10k, 2.5V needs something close to 4k to suppress picking up signals.

Please don't ask me what this board does to signal integrity or relative channel delays, I don't know.

Once the forum allows me to post images and links, I will do so.

Thanks

For now this will have to do.

[attachment=1] [attachment=0]

The resistors will be replaced by 8-element resistor networks, once I've decided which resistances I'll need.

If there is interest, I have 9 PCBs left over. I have headers/jumpers/power cable as well, but no resistor networks / dip switches. All boards were E-tested, so there shouldn't be any surprises. I'll post a link to gerber files and so forth once the 24h ban of external links is over.

Edit: Bare PCB would be 4.50$ + postage.

---

Here's the very simple schematic as well.

I added the 1k series resistors for the voltage lines just in case one should accidentally short out the lines by misplacing a jumper. If you don't need/want them just place a blob of solder on the footprint. It is 0603, so the solder bridge should form quite easily.

I was thinking about something like that, but a more simple version: Just a DIP switch for connecting the signal line to probe or ground line. However, I've never felt the need for this as I don't use RLE. Did you do any tests using RLE? How is the performance?

The one test channel I have working with it right now is quite immune to noise/crosstalk using a 4k-ish pull-up with 2.5V. Going to higher voltages makes it better. Activating a 10k pull-down on the channel works best. In that case I haven't seen any rubbish so far. This was tested using test mode and 200MHz sampling rate + RLE.

As the pull-down variant with 10k resistors seems to work all the time, I've created a board (http://https://github.com/madworm/Openbench_logic_sniffer_pull-U_D_wing) with just that option and nothing else. Board size (width) and part cost are cut down to roughly 50%, which is nice too ;-)

Thanks, usefull Job.

Hi, do you try with 100K resistor? In some situations 10K may be too intrusive (low impedance) for the sniffed circuit.

Not yet ;-)

Unfortunately the coupling between the channels is quite strong. A 100k pull-down is much too weak to kill the crosstalk. I looked at the waveforms on my scope, saw typical RC discharge signals, but was too lazy to use the information any further. I think I could've calculated some rough value for the input capacitance of the pins + wire, knowing the pull-down resistor. Assuming the floating channel gets charged up by a connected channel via some inter-channel capacitance (mainly the wires I guess). It seems with the current setup only 'strong' pull-X resistors are good enough. Using individually shielded probes and GND guard tracks on the PCB would be helpful as well I guess.

Personally I think I will get 4k and 10k resistor networks. And if I should come across a device that can't handle moderate pull-X resistors, I'll curse it and look for a big hammer.

OK, thanks

[quote author="madworm"]As the pull-down variant with 10k resistors seems to work all the time, I've created a board with just that option and nothing else. Board size (width) and part cost are cut down to roughly 50%, which is nice too ;-)[/quote]
Photo?

[quote author="Tarloth"]100K resistor? In some situations 10K may be too intrusive (low impedance) for the sniffed circuit.[/quote]
I made a similar suggestion in the blog entry, but it seems that madworm is only intending to activate the resistors for unconnected probe inputs, and thus there is no sniffed circuit. It's actually a lot easier to design the (pull-down) resistance when you only have to consider the FPGA on one side and not some random, unpredictable circuit on the other side.

[quote author="rsdio"]Photo?[/quote]

As I've already got the 'bigger' one in front of me (which can do the same thing if only half-populated), I didn't have the smaller boards made. It looks like this. The design files are part of its bigger brother's.

Here's what the front side looks like (gerber):

I was actually thinking of making something similar but with few small changes. Since seeed/itead pcb service produces 10 boards I was thinking of making few combinations - 16x (100k, 10k, 4k7, 2k2) and 8x(100k, 10k)+8x(4k7,2k2).

Also the output port instead of SIL I wanted to use the IDC but with cable from PATA drives that has gnd line between all data lines. Have never actually opened the IDC connector for that cable but it should be straight forward like regular idc's.

Arhi:

PATA cables not have GND interleaved with data signals, BUT, all IDC cables interleave upper and down (even and odd) pins of DIL connector. I think that would be better if we replace the SIL connector with a DIL connector with all the extra pins to GND. If we do this then easily put to GND ports simply putting a jumper between even and odd pins. I begin to do this yesterday, when I finish this I put photographs.

In other angle of view. Somebody try to put the FPGA pins to internal pulll down? Maybe the spurios signals in the buffer are weak signals of channel inter talk and not are strong signals and it´s enough putting the FPGA to pull down.

[quote author="Tarloth"]PATA cables not have GND interleaved with data signals, [/quote]

there were 2 types of PATA cables, old 33MHz 40pin cables and "new" 66+MHz/UDMA 80wire cables (they used same 40pin connector only had 80 wires in the cable)

some reference: http://www.pcguide.com/ref/hdd/if/ide/c ... e80-c.html (http://www.pcguide.com/ref/hdd/if/ide/confCable80-c.html)

There's also a wide scsi interleaved cable that might be even more interesting for differential wing :)

Yes, I know ATA 80 pin cables and use it to interconnect dense boards with hi speed signals (they are cheap and standard) BUT you need to design your board thinking in the ATA pin out because this connector internally connects several pin between (all interleave pin with the ATA GND PIN) and has some cables cuted to avoid electric connection.

http://www.allpinouts.org/index.php/Ult ... 66/100_IDE (http://www.allpinouts.org/index.php/Ultra_ATA_66/100_IDE)

With the actual pin out of the OLS I not see how can you use it. But it´s a good thing to think in use something like that to the next OLS version.

as I said I was thinking of making extension board with pull down resistors and IDC connector that would use ATA 80wire cable.

Yes, I read that before, but then the output connector of the extensión board it´s not compatible with the two actual connectors in the OLS board. Instead that you can use a DIL 36 pin connector or simple DIL 40 pin like ATA (more easy to buy) and put all the odd or even pin connected to GND. With that you interleave each signal cable with a GND cable, obtaining the effect that you need without sacrifice connector compatibility.

Yes, that actually makes sense as regular idc does that and "normal size" flat cable with "normal idc" is super easy to source .. as we have 16 pins only anyhow :)

I am still using all 3 LA's at <= 10MHz in 99.9% cases so I don't have issues this board would solve .. and the few times I had to go to 100 and 200MHz scanning frequency I managed to get everything working properly in few tries with some kitchen aluminium foil :D .. was not nice but got the work done

I take today the photographs. Sorry, not high quality but fast, it´s a very very simple change, take me less than half an hour.

I replace the 18x1 connector with 18x2. The second row was connected to GND at both extremes. When I not use some input channel simply put a jumper in this position and put the buffer input to GND. Simple but effective. If I connect a IDC cable to the OLS with this arrangement every data cable it´s interleaved with a GND cable. 

OLS ready to use

Detail at bottom

Detail at top


If in the future exist a OLS 2 version would be very usefull that use two row pin and add other signals to the connector to improve the ols usage.

The GND it´s not perfect when I see with an oscilloscope but not see any phantom glitches in the channels puted to GND, even with the other channels connected to a square wave generator near 10Mhz ones and the clock of the OLS others.

I think this is the best hack of the obls since DP started selling it :D
great idea :)

Thanks, it´s very simple to implement and useful. In next versions of OLS some improvements can be done in this connector to enhance usability.

I have a question? Couldn't this be done through the FPGA, I mean connect the unused signals to GND, by outputting 0s. I have never used FPGAs, but that seems simple enough.

Channels could be grounded, or simply disabled internally. I has been discussed, but very few people are Verilog/VHDL hackers, so nothing has ever happened on that front.

Before add this connector and after that I ask to other users in this thread if the glitchs are strong logic or simple spurios phantom signals at output, I work "touching" the verilog code to see what happens. The glitchs at the output of buffer are strong logic, that it´s, the floating input catch between the input and output signals that trigger a high state at output. If you put the FPGA to 0 in unused channels then the buffer drain too much current from an output to high to the FPGA. It works like a short circuit.  Pull downs after buffer not work because the output it´s really at high state. One solution would be ignore the unused channels in the FPGA at program level, that´s it put a mask (similar to the trigger mask) previous to the RLE algorithm to filter the unused channels and ignore the changes at this inputs. Somebody suggest this in other post I believe. With this the noise problem at unused channels disappear but the cross talking between channels not. If the buffer it´s from a reputable brand the cross talking it´s not a problem, but in next versions of OLS I think that would be a must rethinking the OLS connector to put something more stable.

For example, 2x20 connector as Arhi says would be a huge improvement and it´s cheaper than other options. Grounding each signal in the same form that I use in my simple mod (each signal has his own GND) to permit interleaving signal with GND in a flat cable it´s a good choice. Output to the connector the signals of clocks and permit to select the power voltage to the input of buffer it´s very desirable too.

I think that if we based in something similar to the 40 pin connector of Agilent/ HP Logic Analyzer probes we can´t be wrong. Agilent uses the same connector and the same probes in his Logic Analyzers for 15 years without changes! It works in very old LA and work the same probe too in 2011 LA! I think that work with a similar connector it´s definitively a huge improvement to OLS.

When I end some running projects I work in modifications to verilog code (if somebody with experience in FPGA can do that for us BETTER!) and add the mask to unused channels and work in a form to virtualize the channels used to store in memory ONLY the channels that we use. I think that this is a more efficient management of memory and improves the OLS without changing the clients.

Taking that same principle (grounding un-used pins) i just took a female break away headers and soldered all the connections together; then I just put it on the OLS.

For example, if I use GND-0-1-2-3 then I put the (all connected) female header from 4 down to the end (which is a second ground). That works as well right? The idea is to simple connect all un-used pins to the last ground pin.

When I first got my OLS back in August, I realized the need for something better.  To that end, I did something similar to what Tarloth did, though I used a female header instead.  I arranged this with the top row grounded so that it mates with a castoff pod from an HP 16550.  We've got tons of castoff 16550 stuff at work, since they've long since been replaced with more modern Logic Analyzers like the Tek TLA7012.  I'll post pictures once I get past the new user threshold.

B.B.

Yes, I think that this mod it´s the "natural" mod to do. Do you sell any of the old pod´s? I think that in next version of OLS one of the obligate improvement would be in this connector. Agilent uses the same connector for 20 years, with improvements something like this connector would be a great idea.

Ok, supposedly I should be qualified to post pics now.

Here's the female double row header installed:



And here's the HP16550 data pod connected to the OLS:



As I recall, I did do some rearranging of pins on the HP16550 data pod, but that's really easy to do with the quick-release feature.

B.B.

Exactly!! This is the connector and has a lot of adapters and accesories. This connector works so great that Agilent not change in years.



(From page 33 of http://cp.literature.agilent.com/litweb ... -4632E.pdf (http://cp.literature.agilent.com/litweb/pdf/5968-4632E.pdf))

We can adapt this connector to something more useful for us or simply use the same to maintain compatibility with HP POD´s

What Agilent (formerly HP) calls their "flying lead set" only uses the center 36 pins out of the total of 40.  Pins 1,2 and 39,40 are unused.  Additionally, for the OLS we only need 16 signals with interleaved gnds for a total of 32.  So, I rearranged the pins to make D0-D15 leads connect to pins 35 thru 5 in reverse order to make the channel numbering come out right for the OLS.  Of course I reversed the channel label on the connector too.  The original clk wire is discarded.  So overall, it looks like this:

NC  2     1 NC
GND 4     3 NC
GND 6     5 D15
GND 8     7 D15
GND 10    9 D13
GND 12   11 D12
GND 14   13 D11
GND 16   15 D10
GND 18   17 D9
GND 20   19 D8
GND 22   21 D7
GND 24   23 D6
GND 26   25 D5
GND 28   27 D4
GND 30   29 D3
GND 32   31 D2
GDN 34   33 D1
GND 36   35 D0
GND 38   37 NC
NC  40   39 NC

If you use a 36 pin female header, you can put common gnd leads on pins 4 and 38, but each flying lead end has its own gnd connection anyway.  Since the flying lead set connector is big enough to connect to the 40 pin female header from the HP/Agilent logic analyzer, you have to pay attention to center it on just the 36 pins of the female header on the OLS.  I suppose if I were to do it over, I would've used a 40 pin female header on the OLS, just to make it easier.  The OLS has no place to connect the additional pins.  So, you'd have to remove the extra pins from the connector in order to solder it to the OLS board.

Interesting reading the pdf you cited from Agilent.  Especially the part about the isolation network shown in fig 4.7.  I had assumed previously that the flying lead set was simply straight thru wiring, but after making some measurements, I see that the isolation network is embedded in each of the flying leads.  That is, there is a 250 ohm resistor connected to the flying lead end and that is in series with a 90k ohm resistor that is in parallel with an 8.2pf capacitor.  The 90K resistor is connected to the pod connector.  I don't know how well this isolation network matches the inputs on the OLS, but perhaps it is better than nothing.

B.B.

That´s it! The flying lead connector it´s only passive RC then not need the 5 volt signals at extremes of connector, BUT, other LA connectors use it to connect active POD´s. I remember to use one POD buffer that permit select signals of different electric standard  like RS-232, CAN, RS485, TTL, CMOS, PMOS and other not standard protocols and this POD uses 5 volt to power the circuits. It work similar than the proposal comparator wing but using fet transistor. I use the male connector because I ever use a cable (40 pin standard) between OLS and my only survivor POD and because when use with separate cables it´s easy to short circuit to GND.

I use my  isolation lead with OLS and works like a charm but ringing near 50Mhz. I need to add a 100K pull down resistor to buffer input. I think that if was necessary,  the buffer at input  must be reviewed to permit the use of a general isolation lead (coupling capacities), but many of other buffers use the same pin out and then the replacement it´s direct.

Speaking in therms of Logic Analyzers alone it´s preferable buy an old HP or Tek Logic Analyzer for few dollars than use OLS plus a computer, BUT, the immense advantage of OLS it´s the possibility to implement serial data decoder´s that only expensive LA of this brand´s permit.

My interest in OLS project it´s just that I have something similar to the old 16XXX series (that it´s enough for most of the LA need from hobbyists) with the decode protocols appended. The work with the FPGA in SUMP and specially in Demon Core it´s fantastic and the user that took the 16550 model it´s brilliant. He copy the features of one of the most famous LA and one that still work for several users.

If I can use standard  POD from old LA (plus cheap probes for other uses) then better because old POD´s were pro tools 15 years ago and today still pro with few limits. I prefer to use good tools at end of cables to avoid noise problems (in OLS an inyected in measured circuit) that are very annoying to find.

I have only one POD with the half of flying leads missing and like to buy one in ebay but the shipping cost are bigger than the cost of pod itself to my country.

Are these pods readily available on the used market? I know people buying old HP/Tek logic analyzers often have trouble finding correct pods, and sometimes pay more for the pods than for the analyzer.

I'm convinced that HP did an excellent job on the design of those pods, but I would be worried about the matching of the OLS input impedance (which is probably not very well-behaved) to the RC network. Weren't these designed to be used with the special woven cables?

Matching a popular pin-out sounds like a good idea, as long as it still works with cheap 0.025" connectors (i.e. no Mictor or other exotic stuff). If the OLS were to be changed to match this pin-out, it may also be a good time to add a proper input circuit with some attention paid to signal integrity and maybe even a pull-down somewhere ;).

Alm:

Yesterday I buy a new pod with their flying leads for $35 in ebay and add 20 new original smt probes for extra $20 and the most important, low cost shipping to my country. It´s common to find cheap POD´s and flying leads but not so common find cheap shipping.

But it´s true, an old HP analyzer can be buyed for $150 and the complete POD´s cost more than $200, but it´s true too that with the complete set you have almost 100 input signals, for actual normal not so professional use, 32 input it´s a lot.

I think that it´s good to see standards that was stable in time because they work and probe to be sufficient, perhaps today it´s necessary some adjustments, but essentially maintain the good ideas of the standard. One row of 16 data and one row of 16 GND in a 2x20  0.1" connector (like ATA connector) it´s definitively a very good choice. How we use the extra lines it´s community decision, but use the standard as baseline it´s smart. 

I use the clock input in the POD and buffered it for electric adaptation (5 volt system can´t be direct connected in OLS to external clock). Adapt the total impedance for use "isolate" probes it´s a must, reduce noise and stabilize the probe load in the debuged board. Maintain low the parasitic capacitance too. All of this it´s very cheap to implement and perhaps in the future we can help to improve OLS, I´m offer to work on it.

[quote author="alm"]Are these pods readily available on the used market? I know people buying old HP/Tek logic analyzers often have trouble finding correct pods, and sometimes pay more for the pods than for the analyzer.

I'm convinced that HP did an excellent job on the design of those pods, but I would be worried about the matching of the OLS input impedance (which is probably not very well-behaved) to the RC network. Weren't these designed to be used with the special woven cables?

Matching a popular pin-out sounds like a good idea, as long as it still works with cheap 0.025" connectors (i.e. no Mictor or other exotic stuff). If the OLS were to be changed to match this pin-out, it may also be a good time to add a proper input circuit with some attention paid to signal integrity and maybe even a pull-down somewhere ;).[/quote]

I'm not sure what you mean by "not very well behaved" with respect to the OLS input impedance.  I too was a bit concerned when I discovered that the flying lead set included an RRC matching circuit in each lead.  So, I did some quick sims last night to see what effect it might have.  It was nothing dramatic at all.  Assuming 1.0pf and 100 Meg for the input buffer capacitance/resistance and including the RRC matching circuit, I see only very minor effects.  There was ~2db of attenuation at 1 GHz.  I don't expect nor have I encountered any issues with using the HP/Agilent flying leadset since last August.  200 MHz captures work fine and compare favorably with captures from state of the art high end logic analyzers.  Having a gnd pin at each probe end is an absolute must for high speed work.

On the subject of pinout for the OLS, I absolutely do not recommend any pinout change for the OLS.  The HP/Agilent flying lead set is ridiculously easy to rearrange the pins to an OLS compatible pin arrangement.  The only change that I'd recommend for the OLS, is to support a double row female header, keeping the basic pinout the same.

B.B.

[quote author="Qwlciguk"]I'm not sure what you mean by "not very well behaved" with respect to the OLS input impedance.
[/quote]
What I mean is that I don't expect the impedance to be very flat across the frequency spectrum, since it's just an unterminated input straight into the buffer, without any form of damping or termination. Maybe even some resonance in the pass band. The HP RC matching network might help, although I expect their front-end to be much better given their RF background. Agilent scope inputs also tend to be better in this regard than other manufacturers.

[quote author="Qwlciguk"]
I too was a bit concerned when I discovered that the flying lead set included an RRC matching circuit in each lead.  So, I did some quick sims last night to see what effect it might have.  It was nothing dramatic at all.  Assuming 1.0pf and 100 Meg for the input buffer capacitance/resistance and including the RRC matching circuit, I see only very minor effects.  There was ~2db of attenuation at 1 GHz.[/quote]
This is not something I'd trust a simulator on. I highly doubt the 1pF spec, the PCB trace alone is probably more than that. -2dB at 1GHz would be extremely impressive, since scope vendors on the market never (?) succeeded in making a useful 1 Mohm front-end beyond 500MHz, it's all 50 ohm above that.

But if it works for you I guess that's all you should care about.

[quote author="alm"][quote author="Qwlciguk"]I'm not sure what you mean by "not very well behaved" with respect to the OLS input impedance.
[/quote]
What I mean is that I don't expect the impedance to be very flat across the frequency spectrum, since it's just an unterminated input straight into the buffer, without any form of damping or termination. Maybe even some resonance in the pass band. The HP RC matching network might help, although I expect their front-end to be much better given their RF background. Agilent scope inputs also tend to be better in this regard than other manufacturers.

[quote author="Qwlciguk"]
I too was a bit concerned when I discovered that the flying lead set included an RRC matching circuit in each lead.  So, I did some quick sims last night to see what effect it might have.  It was nothing dramatic at all.  Assuming 1.0pf and 100 Meg for the input buffer capacitance/resistance and including the RRC matching circuit, I see only very minor effects.  There was ~2db of attenuation at 1 GHz.[/quote]
This is not something I'd trust a simulator on. I highly doubt the 1pF spec, the PCB trace alone is probably more than that. -2dB at 1GHz would be extremely impressive, since scope vendors on the market never (?) succeeded in making a useful 1 Mohm front-end beyond 500MHz, it's all 50 ohm above that.

But if it works for you I guess that's all you should care about.[/quote]

We're not trying to make a commercial instrument here.  The OLS only goes to 200 MHz sample rate.  I only did the sim to see if some nasty stuff would happen in the 10-500 MHz region.  I'm very much aware that sims need to include full characterization of all parasitics in the complete path.  If the sim had shown problems with just a simple model, then I'd stop immediately and question why I was getting good results in the real world.  After I get back to work next week, I can do a full TDR characterization on the path, but from long experience with doing this stuff, I don't expect any big revelations.  I can also make measurements with a high-speed scope right at the buffer pin with an ultra-low capacitance (<1.7pf) 3GHz bandwith probe. As for the 1.0pf, the pin capcitance itself is probably a fraction of a pf, though the input buffer stage adds another 3-5pf to that.  Playing with the load cap in the sim doesn't change things much.  Remember that there is an 8.2pf cap in parallel with the series 90.9K resistor and this offsets the effects of the load cap.  A trace on a 2 layer PCB with no gnd plane and large spacing to other traces, tends to show more inductance than capacitance.  If there's a problem with the sim model, it's the non-inclusion of parasitic inductance, not under-estimation of capacitance.

B.B.

I'm not saying there are issues, just that I wouldn't expect it to be very well behaved. I may well be wrong. Your measurements definitely trump my impressions. A useful test might be to feed it some fast edges and observe the signal at the FPGA pin. This should give a good idea of signal integrity and cross talk. Main interest in my opinion would be without the pod, since most of the users won't be using the pods, and they may compensate for some issues.

If there's no ground plane (I didn't check the layout), then you're correct about the trace capacitance, I had automatically assumed a PCB designed for ~200MHz to have a ground plane. The buffer is likely an important component unless you use the unbuffered 'wing' input.

.. some topics on probes and impedance matching from past:
viewtopic.php?f=23&t=1841 (http://dangerousprototypes.com/forum/viewtopic.php?f=23&t=1841)
viewtopic.php?f=23&t=1819 (http://dangerousprototypes.com/forum/viewtopic.php?f=23&t=1819)
viewtopic.php?f=57&t=1798 (http://dangerousprototypes.com/forum/viewtopic.php?f=57&t=1798)
viewtopic.php?f=57&t=1813 (http://dangerousprototypes.com/forum/viewtopic.php?f=57&t=1813)
viewtopic.php?f=23&t=2274 (http://dangerousprototypes.com/forum/viewtopic.php?f=23&t=2274)
miro

Miro:

I have been read this post and I think that you have a very accurate point of view. Of reading those post I think (my opinion off course) that something was OK and something wasn´t, in general:

* Simulation of physical data path: If I something learn in twenty years of work with signals it´s that the simulations of this stuff never wasn´t totally correct unless we have the exact physics behavior of cable plus connector plus PCB and then with this secure data then model the circuit at point to optimize the data path, or, have the exact behavior of probe plus cable plus connector and then design the PCB, select the buffer  and model the RLC circuit before buffer. Maybe we need to do some commitment between them to improve matching to a vast variety of possible probes, from a unshielded bare cable (today seedstudio probes) to a compensate clip (profesional POD´s).

* Signal degradation: instead of previous point, Logic Analyzer NOT ARE oscilloscopes, then signal shape degradation it´s irrelevant to the extend that the time shifts would be minimize, ringing not bother if it is less than signal threshold and it important to maintain the crosstalking avoided. With this in mind, we need to control that the relative phase between the input signal at the probe and the input signal at FPGA would be constant through bandwidth and uniform in all channels. Control the total electric path it´s important, reduce jitter the first goal and not bother if the isolation circuit destroy the upper limit frequencies that forms the cusp borders of rectangle signals a must.

* Using probes with proper matching for high speed use: I need that, I observe signals at 50Mhz (at least) and need to avoid disturbances to the debugged circuit. For that I use the pod of Agilent, a very good stuff, cheap if you buy at ebay or used to somebody that not use the LA anymore. High impedance and low reflection it´s a must for this cases. Although, I think that 95% of OLS users are very happy with the probes sold by seedstudio or use something like I use in slow signals that are cables with female connectors in each point (perhaps a ferrite at middle) and are better to fix to board in regular pines and that it´s OK, it´s mad to force use a $50 probe to inpect a 10 KHz signal!. I think that it´s necessary a commitment between two worlds. Its important  to do some pull down, impedance and electric path improvement to OLS board that benefit both extremes. I know that this it´s not perfect but the OLS live in middle of this worlds. By now works, with some precautions work without matched and works good I f we think that entire LA cost less than a good probe!

* Socketed Buffer?: If we made something wrong and damage the buffer (their main function, protect the FPGA) I think that it´s good if we can replace without the pain of desolder and resolder the chip to board. I don´t know ow many OLS users have the appropriate solder station to guarantee a good job that not damage the board. 

* Buffer the Clock (in and out) and trigger (in and out) too. This it´s important. Today if I need to use an external clock to OLS from a 5 volt system need to adapt the signal.

* Input voltage threshold: I think that it´s necessary to work at this point. Comparators sound good if they have a uniform propagate time and permits working with signals in the +- 12 volt range (almost).  For example, last week I need to inspect the sequence of signals at 16 bipolar transistor bases. Signals are 0 volt to 0.8 volt aprox and need to view the signals with the actual timing shift that it´s not seed in the TTL signals that excites the analog circuit that manages the transistors. I need this fast and without time to build any circuit, then use my 4 channel oscilloscope to inspect groups of 5 transistors, but OLS have been the correct choice to do that. Using 1.8, 2.5, 3.3 and 5 volt logic (and perhaps old CD4000 levels) should be easy of select without to much trouble to improve the OLS use.  But which percentage of users need this? Perhaps implements an active POD with this characteristics connected to a standard buffered input? If somebody not need that, uses the base OLS connector, but if other one need this, connect a POD with some circuitry that speaks to OLS in terms o 3.3 volt logic? That it´s used by mayor brands in cases like differential signals or "strange" electrical levels like CAN, RSXXX, etc. For this a connector like Agilent permit do that since have power supply and frankly I don´t like to use the wing expansion, really prefer to 16 buffered signals connector and uses the correct POD in each case.

I think that all of this things would be reviewed to the next version of OLS, meanwhile the board it´s great and full of uses and behaves remarkably well. I still amazed with OLS in price/performance but with few dollars I think that this would be improved

Finally found the time to do some scope pictures with the 16550 probes.

The equipment:

Lecroy 20GS/s digital scope
Lecroy single-ended low capacitance probe (2.5 GHz rated, 0.7pf, 100K)

The signal being measured is ~30 MHz 1.8V logic level square wave.

Here's what the signal looks like at the source with the low capacitance probe:



And at the input to the LCX16245 buffer on the OLS with the same low capacitance probe:



A couple of things to note here.  The low capacitance probe is significantly altering the circuit due to the 100k ohm input impedance.  Remember, there is a 90k ohm series resistor in the 16550 probe tip.  So, that forms a voltage divider that attenuates the signal ~2:1.  Also, there is significant baseline shift seen as the signal does not get anywhere near ground.  This is due to a mis-match between the 8.2pf capacitor paralleling the 90k resistor in the 16550 probe tip and the load capacitance after the probe tip and all the way back to the OLS input.  The original 16550 design has a very large load capacitance on the order of 75pf, while our OLS + 16550 cable is much less, on the order of 15pf.  The ratio of the probe capacitor to the load capacitance should match the ratio of the series resistance to the termination resistance.  If it doesn't, you'll see the baseline shift that we have here.

The obvious thing to do here, is to decrease the termination resistance.  The 16550 design is using a 10k ohm termination resistance, yielding a 10:1 attenuation.  That's not going to work for the OLS since we don't have inputs that can deal signals that have been attenuated to that extent.  Fortunately, we can come up with a termination resistance that matches the 8.2pf : 15pf ratio.  15/8.2 = 1.8 and 90k / 1.8 = 49.2k.  If we want to look at the signal with the low capacitance probe, we've already got 100k termination resistance.  So, we can simply add another 100k in parallel and see what it looks like.

See the picture below with 50k effective termination resistance:



Here now we can see the baseline shift has gone away almost entirely and the signal comes close to ground on the low side.  That is confirmation that we've got the proper matching term resistance compared to the ratio of series capcitance to load capacitance.  Unfortunately, we've also got almost a 3:1 attenuation of the input amplitude.  In fact, the signal does not even go high enough to be seen as a logic '1' by the OLS.  All is not lost though.  We can connect the term resistor to a voltage above gnd, biasing it near the 1.5V threshold such that the signal swings symmetrically above and below the 1.5V threshold of the LCX16245.  Oddly enough, tying the term resistor to a 1.833V low impedance source, will accomplish that.  We'll get about +/- 300mv swing above and below the threshold.  I can't measure the final result directly since the low capacitance probe is single-ended and one leg has to be tied to gnd and not the term voltage, but I did verify with static DC voltages of +1.8 and 0V input that we get 1.8V and 1.2V at the OLS input.  Just what we want.

Of course, the 1.8V termination voltage is only correct for a 1.8V logic level input.  For 5.0V, 3.3V or 2.5V, we'll need  different terminating voltages.  For 5.0V, 0.944V term voltage centers the swing nicely on the 1.5V LCX16245 threshold.  Similarly, for 3.3V, 1.42V works nicely and for 2.5V logic input levels, 1.64V is perfect.

I have done these mods to my OLS.  I added sixteen 49.9k resistors to the 16 inputs at the connector with the other end of the 16 resistors all bussed together and bypassed to gnd with four 0.01uf X7R caps evenly spaced over the length of the connector.  I added a jumperable low impedance voltage divider for a selectable logic threshold, (ie 5V, 3.3V, 2.5V, 1.8V) and this connects to the common end of the 16 term resistors.

It's all working quite well and it gives me some ideas for doing an add-on wing.  I'd want to use something better than the LCX16245 for sure.  Probably something with SSTL inputs.  Also need something other than a 16550 pod, since these aren't going to be available to the masses at a reasonable price.  Simple wires, shielded or not, are not going to cut it.  We absolutely need an input isolating network like the 90k/8.2pf in the 16550 probes.

If I get a chance, I'll do a picture of my modded OLS and post it here.

B.B.

EXCELLENT!

Can you post a schematic too? It´s more clear to ask. Thanks. I have a question, it´s not more stable to use some of the new dual supply translating buffer like the 74ALVC164245 (from NXP, although limited to 100Mhz, exist other parts to +200 Mhz)? I use these parts to scan buses with different VCC and works like a charm, every threshold was correct without need to float the signal and are really cheap. Simply change the second VCC with a jumper to the level that you like to scan and all it´s OK.

Have you measured the differences in the propagation time between the inputs with the 16XXX probe and the FPGA input?

Thanks again for your effort to have a better OLS.

Here's the schematic.

I have used dual voltage translating buffers for other applications, but I don't see how to apply them here, since with a 1.8V logic input swing, after the unavoidable voltage divider formed by the 90.9k series resistor and the 49.9k termination resistor, we only have ~600mv of voltage swing at the buffer input and that's not going to work well with dual supply translating buffers.  If you drop the voltage enough to make that work, the propagation delay becomes very large.

Given free reign to design something to do this ideally, I'd use an SSTL type buffer which are specifically designed for precise threshold detection.  Still have to use the variable termination voltage to deal with different logic voltage levels (ie 5V, 3.3V, 2.5V, 1.8V).  FWIW, I noticed that the "wing" inputs can be configured at design time for SSTL input characteristic.

B.B.

---

but I don't see how to apply them here

For example, using the 74AVC16T245 yo can obtain the threshold for 1.8 volt if VCC it´s 0.8 volt and other input threshold varying the VCC, they work to me better that other solutions and it´s cost effective (propagation time in next paragraphs), but I follow you with this and never tray SSTL2 logic to do this. I love to test everything that seems good or interesting and you take this seriously. Do you have in mind any part to put in replace or companion of current buffer?

If you drop the voltage enough to make that work, the propagation delay becomes very large.

YES! That its VERY true, but I assume that only a small fraction of users use OLS at really high speed. For example, the part that I random select (maybe with carefully search this would be improved) at lowest VCC (0.8) has a propagation delay of 15ns that limits OLS to 60 Mhz and it´s ugly, but at 1.1 volt (2.5 volt at inputs) has  7nS of delay. I not read about buffers of Texas in last years, but someone in laboratory uses their low voltage series up to 300Mhz, I dont know which is the High input threshold. The advantage of using this translators it´s that we can direct replace the buffer in the current board with very low changes.

Thanks for the schematic

[quote author="Tarloth"]

but I don't see how to apply them here

For example, using the 74AVC16T245 yo can obtain the threshold for 1.8 volt if VCC it´s 0.8 volt and other input threshold varying the VCC, they work to me better that other solutions and it´s cost effective (propagation time in next paragraphs), but I follow you with this and never tray SSTL2 logic to do this. I love to test everything that seems good or interesting and you take this seriously. Do you have in mind any part to put in replace or companion of current buffer?

If you drop the voltage enough to make that work, the propagation delay becomes very large.

YES! That its VERY true, but I assume that only a small fraction of users use OLS at really high speed. For example, the part that I random select (maybe with carefully search this would be improved) at lowest VCC (0.8) has a propagation delay of 15ns that limits OLS to 60 Mhz and it´s ugly, but at 1.1 volt (2.5 volt at inputs) has  7nS of delay. I not read about buffers of Texas in last years, but someone in laboratory uses their low voltage series up to 300Mhz, I dont know which is the High input threshold. The advantage of using this translators it´s that we can direct replace the buffer in the current board with very low changes.

Thanks for the schematic[/quote]

If not using the 16550 input probes, then a dual voltage translating buffer replacing the one on the OLS is a reasonable thing to do.  That will allow operation with 1.8V logic input signals, where the existing LCX16245 is a little marginal.  2.5V and 3.3V logic should be no issue with the current LCX16245

For my application using the 16550 probe set, the AVC16T245 will not work due to the excessive propagation delay at the very low voltage that I'd have to use for the input supply voltage.  With 1.8V logic levels, the signal gets attenuated down to only 600 mv or so at the termination resistor.  The minimum VDD for the AVCT16245 is 1.2V and prop delay at that voltage is quite large, but more importantly, I'd expect that the variation from buffer to buffer in the same package, to get larger too.  I'd still have to bias the termination resistor to get the input voltage swing centered around the input threshold.  So, for the 16550 probe application, replacing the existing AVC16245 with a dual supply tranlator, doesn't do anything but add more prop delay/variation.

I believe that TI has other dual voltage translators that work down to 0.65 volt supply. Still, the ideal design for the OLS application is SSTL.  With that, we get a 0.9V or 1.25V threshold with only a very tiny (+/-100mv) input voltage swing required.  Those threshold voltages are are designed for 1.8 and 2.5 volt logic levels respectively.  If you re-compile the OLS specifying SSTL inputs for the unbuffered "wing" inputs and then provide the 1.8 or 2.5V I/O supply for those pins and supply an appropriate Vref (0.9V or 1.25V), you would have low voltage compatibility without any added propagation delay/variation.  You'd need a few jumpers on the board to select the supply and Vref, but all in all, it would be just a small change to the existing OLS design.

B.B.

I´m using the 16XXX probe too but in 5 volt, I have an old one and now buy a new one because they are great for the cost, but it´s true that is not cheap, but isn´t so expensive if you need a good probe.

How bad it´s in the real life use a resistance of 100K instead of 49.9K? With that someone not need to make a wing, only change the buffer and the things can work (replacing the buffer off course).

Here's a picture of the termination mod for the 16550 probes:



The hot melt glue is not actually holding down the single row header (that's soldered to the gnd plane).  It's just there to protect the resistors and wiring on the header from getting damaged when handling.

B.B.

[quote author="Tarloth"]I´m using the 16XXX probe too but in 5 volt, I have an old one and now buy a new one because they are great for the cost, but it´s true that is not cheap, but isn´t so expensive if you need a good probe.

How bad it´s in the real life use a resistance of 100K instead of 49.9K? With that someone not need to make a wing, only change the buffer and the things can work (replacing the buffer off course).[/quote]

If you only work with 5 volt logic, then using 100K termination resistors will work with no need to change the buffer itself.  Even with the 2:1 attenuation and baseline shift, it will probably work OK.  If you work with lower voltages (3.3, 2.5, 1.8), then you may run into trouble due to the attenuation and baseline shift.  You may get lucky and have the baseline shift move the voltage swing upward enough that the smaller signal swing still crosses the 1.5V threshold of the input buffer.

B.B.

B.B.:

I not only work with 5 volt, but at the moment I have not choice when work with HP probes. I like in the near future (before OLS 2.0) to work with other signal level, and in fact, 3.3 volt it´s the facto standard that I use. With the 1/3 attenuation, I have control of line from 3.3 to 5 volt (vcc to part 1.5 volt and 2.5 respectively) using an other buffer solder instead actual buffer and perhaps 2.5 volt. Using 1/2 attenuation I have the entire range, but need to measure at work the final waveform for check to excessive ringing.

Other option it´s to build a wing for work specifically with Agilent probes or something with the same characteristics and then use your improved suggested circuit or perhaps the comp circuit suggested in other posts.

Where you live? If we do the wing I can send you the PCB or even the circuit with components soldered for free.  Everything open source off course and published here.