Title: [Entry] Discrete logic amplifier
Post by: haley0918 on October 20, 2011, 06:21:17 am
Post by: haley0918 on October 20, 2011, 06:21:17 am
This is my second entry for the 7400 logic competition. It’s a discrete logic amplifier made of mostly discrete logic chips. This amplifier is a continuation of my previous discrete logic preamp (http://http://dangerousprototypes.com/forum/viewtopic.php?f=62&t=2986). The main objective here is to amplify the input signal to a suitable level for driving a buzzer or other voltage driven application.
The amplifier works by converting the analog signals into digital form. The converted digital data is then feed through a logic level converter to bring the digital data to a higher voltage level. The digital data then converts back to analog signal but with larger amplitude.
The circuit consists of a delta-encoded ADC with a feedback R2R DAC, logic level converter using two sets of buffers, a crystal oscillator and another R2R DAC for final output. There are two 74LS169N four bits binary counters cascaded as 8 bits with a LM361 fast comparator that forms the ADC part. The fast comparator compares the input with the feedback and outputs logic high or low that causes both counters to count up or down. The 8 bits output of the counters goes through the first set of R2R DAC to form back as analog feedback. Because of the simple ADC design, the output theoretically will always oscillate by one bit assuming a stable input.
The crystal oscillator was made of 74LS04N hex inverter and clocked at 40MHz to allow headroom for higher frequency analog input sampling. Operating at such frequency, the counters will take 6.4us to count from 0 to 256 or about 156kHz ramp when probed at the DAC with no feedback and counters' direction fixed. When Nyquist rate was considered, this allows us to sample input frequency up to about 78kHz so that the counters could always catch up and won't cause distortion at output.
The 8 bits output of the counters also goes through the logic level converter which consists of 8 TTL to CMOS logic converter (2 x 74LS07N) and 8 CMOS buffers (2 x 4050N). The key here is that CMOS logic chips are capable of higher operating voltage (up to 15V compare with TTL 5-7V) and this is where the actual amplification takes place. Volume adjustment could be done by varying the supply voltage to the CMOS buffers but was not implemented in this entry. The amplified 8 bits then goes through the second set of R2R DAC to convert back to analog signal but with larger amplitude.
Breadboard prototype
This video shows the amplifier's response to analog signal varied by a potentiometer.
http://http://www.youtube.com/watch?v=raYhhJn8MQQ
Lastly, the preamp and amplifier were put together to operate.
Video below shows the piezo signals picked up by preamp and amplified to a buzzer.
http://http://www.youtube.com/watch?v=6GRiSdUaoU4
The amplifier works by converting the analog signals into digital form. The converted digital data is then feed through a logic level converter to bring the digital data to a higher voltage level. The digital data then converts back to analog signal but with larger amplitude.
The circuit consists of a delta-encoded ADC with a feedback R2R DAC, logic level converter using two sets of buffers, a crystal oscillator and another R2R DAC for final output. There are two 74LS169N four bits binary counters cascaded as 8 bits with a LM361 fast comparator that forms the ADC part. The fast comparator compares the input with the feedback and outputs logic high or low that causes both counters to count up or down. The 8 bits output of the counters goes through the first set of R2R DAC to form back as analog feedback. Because of the simple ADC design, the output theoretically will always oscillate by one bit assuming a stable input.
The crystal oscillator was made of 74LS04N hex inverter and clocked at 40MHz to allow headroom for higher frequency analog input sampling. Operating at such frequency, the counters will take 6.4us to count from 0 to 256 or about 156kHz ramp when probed at the DAC with no feedback and counters' direction fixed. When Nyquist rate was considered, this allows us to sample input frequency up to about 78kHz so that the counters could always catch up and won't cause distortion at output.
The 8 bits output of the counters also goes through the logic level converter which consists of 8 TTL to CMOS logic converter (2 x 74LS07N) and 8 CMOS buffers (2 x 4050N). The key here is that CMOS logic chips are capable of higher operating voltage (up to 15V compare with TTL 5-7V) and this is where the actual amplification takes place. Volume adjustment could be done by varying the supply voltage to the CMOS buffers but was not implemented in this entry. The amplified 8 bits then goes through the second set of R2R DAC to convert back to analog signal but with larger amplitude.
Breadboard prototype
This video shows the amplifier's response to analog signal varied by a potentiometer.
http://http://www.youtube.com/watch?v=raYhhJn8MQQ
Lastly, the preamp and amplifier were put together to operate.
Video below shows the piezo signals picked up by preamp and amplified to a buzzer.
http://http://www.youtube.com/watch?v=6GRiSdUaoU4