Just in case this helps anyone else. I'm still playing with the first CPLD project I have tried, a basic start-stop counter running with 50 MHz onboard clock. You can see the schematic, pinout and other documents here:
http://bealecorner.org/best/measure/time/CPLD-TIC/ (http://bealecorner.org/best/measure/time/CPLD-TIC/)
I was seeing flaky behavior; it seemed the timer would not always stop correctly. I would send a STOP signal input, and the latched STOP_S3B output would be just a 10 ns glitch, instead of the clean logic edge expected. Scope photo:
https://picasaweb.google.com/1099282360 ... 5466304466 (https://picasaweb.google.com/109928236040342205185/Electronics#5661381005466304466)
I found the RESET input line shows a serious glitch when the STOP_S3B output goes high. It is supposed to be driven low by an external circuit during that time, but in fact it has about 2.7Vpp noise as seen with a 10x scope probe. Scope photo:
https://picasaweb.google.com/1099282360 ... 5397111154 (https://picasaweb.google.com/109928236040342205185/Electronics#5661741415397111154)
Switching my scope probe to 1x added enough capacitance to the RESET pin to make the circuit work (almost) all the time. The indicated noise level was reduced to 0.6Vpp (not accurate, since my probe has much reduced bandwidth at 1x).
The scope says the +3.3V and +1.8V supply rails on the CPLD board have very little noise. The reset line was being driven by a PIC32 pin (Digilent Uno32 board), typical 3.3V CMOS level output I think.
Then I realized I was just being stupid about my signals. I had the STOP_S3B output signal right next to the RESET input signal, through 6" of ribbon cable (and no ground in between). Photo: https://picasaweb.google.com/1099282360 ... 0196560034 (https://picasaweb.google.com/109928236040342205185/Electronics#5661900600196560034)
That was enough capacitive coupling from output to input to do me in (the edge risetimes from the CPLD are just a few ns, which my 60 MHz scope can't accurately measure.) I measured a similar 12" length of 2 strands of ribbon cable to be 14 pf. When I just pulled the two strands of cable apart, my glitch amplitude dropped by about half. The remaining noise is as the same level as the switching noise while the various counter outputs are driving the ribbon cable. I think better design would have a separate shift register for output, rather than parallel out direct from the counter.
(Note, I got some useful suggestions from the xsboard-users Yahoo groups mailing list, although that's really for different hardware; FPGA boards from XESS corp.)
Have you tried playing with the programmable slew rates? That might have helped but not sure.
I didn't try changing the slew rate, but there's only two settings and "slow" is at most a factor of 2 slower than "fast". I think better wiring is the way to go :-)