Dangerous Prototypes

Hi Guys,

I have an existing CPLD with a program - a BK precision was used to extract the .jed file from it. do you guys know of any way to convert that to SVF and then to xSVF so that i could program a new one with the BusPirate?


Thanks
Philip

you should be able to convert JED to (x)SVF with ImPACT

yeah i already tried opening the .jed file from impact but it shows an error on adding the device. What could this error mean?

what did the error show. Maybe the JED is not correct, maybe you tried to do soemething wrong in impact, maybe .... try to capture the error and paste here

here are the error and the jed file ide like to open. The Jed file was saved as .txt so that i could send it here

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your JED file is wrong. Linux version of impact show bit more errors

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This jed file was read from a frequency counting CPLD. I dont have the code for it i guess i really need to program it from the start. :(

Have any idea how to implement a frequency counter in a CPLD?

open that JED file - it's full of zeros .. only few bytes populated so I don't think you extracted the data properly.

As for how to do a freq counter ..
for e.g. http://ad7gd.net/counter/ (http://ad7gd.net/counter/) :

// High-speed counter with serial output.
//
// Usage:
// 1.  Connect input signal to clk, everything else to microcontroller.
// 2.  Reset the counter.
// 3.  Bring ce high to start counting.
// 4.  If desired, wait for 'counting' to go high to synchronize gate to slow input.
// 5.  Wait for counts to accumulate (make sure Fmax can't overflow CTRWIDTH).
// 6.  Bring ce low to stop counting.
// 7.  If desired, wait for 'counting' to go low to synchronize end of gate.
// 8.  Read LSB from sdata,
// 9.  Strobe sclk, read next bit, repeat.
// 10.  Frequency is ctr / gate_time.
module top(clk, ce, rst, sclk, sdata, counting);
	input clk;
	input ce;
	input rst;
	input sclk;
	output sdata;
	output counting;
	
	parameter CTRWIDTH = 28;
	
	reg [CTRWIDTH-1:0] ctr;
	
	always @(posedge clk or negedge rst)
		if (~rst) ctr <= 0;
		else if (~ce) ctr <= ctr;
		else ctr <= ctr + 1;

	reg counting;
	
	always @(posedge clk or negedge rst)
		if (~rst) counting <= 0;
		else if (ce) counting <= 1;
		else if (~ce) counting <= 0;

	reg [4:0] index;

	always @(posedge sclk or negedge rst)
		if (~rst) index <= 0;
		else index <= index + 1;

	assign sdata = ce ? 0 : ctr[index];

endmodule

There's also example from Xilinx (for fpga with lcd and all but you can extract vhdl for counter only and implement into your cpld as it's the same code): http://www.xilinx.com/products/boards/s ... ounter.zip (http://www.xilinx.com/products/boards/s3estarter/files/s3esk_frequency_counter.zip)