Hi any one has an idea on how to implement a frequency counter in 9572XL?
there are two ways to measure frequency,
1> measure the time it takes one cycle to complete
2> count the cycles in an fixed known duration
either way you will need a counter and a reference frequency.
you have 2 examples in the "other" theme you opened about this :)
Cool project, thanks a lot for sharing it.
Jan
@jason - thanx for really nice design.
Wonder, which parts of the design are most resource consuming.
I have on hand the XC9536XL (64 pin package) that I would like to use as frequency counter.
It should work above 100 Mhz.
Perhaps LED display control could be moved away to MCU.
Time sources could also be easily outsourced.
Do you think this concept could work on this 36-cell chip ?
And how would it perform, if I would offload 7 segment display and gate clock all together ?
The design would contain decimal divider(s) only.
So the maximum speed will be limited to first flip-flop.
My 9536XL -10 has 100 MHz limit because of 10 nS pin to pin delay.
But with this design this is not so important.
Have you tested maximum frequency of 9536's flip-flop ?
[quote author="jason"]I did test the maximum frequency of the 9572-10, and it was just below 100Mhz.[/quote]
What (and how) exactly have you tested ?
Datasheet of 9500 family states that for 9572:
fSYSTEM = Internal operating frequency for general purpose system designs spanning multiple FBs is 83,3 MHZ, but
fCNT = Operating frequency for 16-bit counters is 125 MHz.
respectively for 9536:
fSYSTEM = 100 MHz
fCNT = 100 MHz
These parameters are probably not relevant to our case (one flip-flop only). More suitable would probably be:
TPD, TSU, TCO.
and here for 9572:
7.5, 4.5, 4.5
but for 9636 they look better:
5.0, 3.5, 4.0
all nS values.
For the dividers only design what really matters is the speed of a first flip-flop which divides frequency by half (to the safe levels).
Do you know how to design this CPLD (which cell to use first and so on) to achieve highest speed ?
@jason
90 MHZ you have received in your tests is not a satisfactory result for this device (I guess).
I was digging a little bit around this performance topic, and found that the maximum speed limit is far above 90 MHz.
Just studied DS064 and DS058 datasheets, and am confused.
So, in DS064 page 4 I found Fsystem = 66,7 MHz and Fcnt = 111,1 MHz both stated as minimums for XC9536-10 (5Volt device).
But DS058 on page 4 provides Fsystem = 100 MHz as maximum for XC9536XL-10 (3,3Volt device).
With above mentioned speeds, could I expect Fcnt (which is also Ftog of the flip-flops) to reach almost 200 MHz on XC9536XL-10 (3,3Volt device) ?
@ jason
Wonder how far would change to crystal speed improve the range of a counter.
I guestimate that if you would replace 1 MHz crystal with 32 kHz one, then you would gain resources for one or maybe two additional digits for the display in your counter.
Do you think this type of crystal would be precise enough for this type of application ?