Dangerous Prototypes

Dangerous Prototypes => Bus Blaster JTAG debugger => Topic started by: tayken on June 28, 2011, 07:37:24 pm

Title: Bus Blaster FPGA programming
Post by: tayken on June 28, 2011, 07:37:24 pm
Hi guys!

I was wondering if anybody used Bus Blaster for FPGA programming. The problem I have now is that I cannot program the board I have. I use the general CPLD tutorials, I generate a .bit file in the end (synthesis). I'm sure that I have to do sth else with IMPACT as svf file generated cannot be loaded, it just gives an error. "detect" and "print chain" commands work, but I know that I have to upload the file to the EEPROM, but got a little confused there.
Title: Re: Bus Blaster FPGA programming
Post by: ian on June 28, 2011, 08:24:08 pm
Hi Tayken,

Can you please describe the setup (chips) and how you use IMPACT? Are you using the alt-linux driver (I'm guessing)?
Title: Re: Bus Blaster FPGA programming
Post by: tayken on June 28, 2011, 08:44:20 pm
OK, it is this (http://http://www.marutsu.co.jp/shohin_65177/) board (Japanese link warning). It has a XC3S250E-4VQ100C FPGA and a XCF02SVO20C PROM.

I'm not using the alternative driver, I didn't install cable files so I cannot use alt-linux drivers (I'll try to install cable drivers and give it a try probably tomorrow). Basically I'm trying to follow your CPLD tutorials but I cannot add the ROM to chain. So what I did was follow up the tutorial about exporting svf files. I then try to upload it with urJTAG which gives an error about some mismatch.

I'm guessing I have to install the cable drivers and use alt-linux drivers directly with IMPACT. Just wondering if there is an alternate way.
Title: Re: Bus Blaster FPGA programming
Post by: ian on June 28, 2011, 10:42:11 pm
Quick guess  you need to add rom to the chain. - for Rom programming you usually use a bit file.

Can you detect the fpga with urjtag? If so, you can find bsdl file and add it to the chain. I tinwk you still need to accunt for the ro. Though eith a bypass instruction. Sorry for mobile device spelling issues.
Title: Re: Bus Blaster FPGA programming
Post by: tayken on June 29, 2011, 05:09:18 pm
I was able to detect the whole chain, I have to run bsdl command first but it detects just nice.

I ran "part 0" command before svf, now I am able to program the FPGA. It lights up the LED (test program just does this) but when I unplug the JTAG connection, it just stops. At least there is little progress.
Title: Re: Bus Blaster FPGA programming
Post by: tayken on June 29, 2011, 05:15:21 pm
Partially solved!

After svf command, I ran "instruction BYPASS" and "shift ir" and it works now. As long as I do not unplug the power or the JTAG connection, it seems it is ok.
Title: Re: Bus Blaster FPGA programming
Post by: tayken on June 29, 2011, 06:17:52 pm
Fully solved!!!

I had to create a mcs file for PROM in IMPACT. Then I just export the mcs file to an svf file and select PROM with "part 1", load svf file, "instruction BYPASS" and "shift ir". This way the program runs even when I unplug the JTAG connector or remove power. :)
Title: Re: Bus Blaster FPGA programming
Post by: ian on June 29, 2011, 06:27:19 pm
I'm glad you got it, I like how you said Then I just... ;) JTAG iz hard :)
Title: Re: Bus Blaster FPGA programming
Post by: tayken on June 29, 2011, 06:44:20 pm
Over the weekend I'm planning to create a How-to document with screenshots and such. I can decipher what I wrote here by myself but for others it might be hard. :) Sometimes even I can decipher my notes! :D

Exporting mcs file to svf: Basically the same stuff you do with jed files in CPLD tutorials, but this time you select mcs files.

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