this project wont be done next week, nor even next month.
its a summer holiday project so i will seriously start with it after 4 juli when my 7 weeks of nothingness begins :D
i hope its OK to post a not done project, i will add stuff while making it so i end up with a good log of the whole project.
I want to make a USB scope, but you could have guessed that from the title.
I also want to make it quite cheap, I aim for 50 euro's to make one
as a school project we are already making a simple scope but its rather limited in speed and use, 1Msps is kinda slow :)
but we got the scope part working, only the software is left to do.
but 1Msps is really not useful, effective bandwidth for looking at a sine wave is maybe 50Khz.
Then i saw the scope project from DP(Dangerous Prototypes)
That looks a lot better, 50Msps means 3 to 5 MHz usefulness bandwidth for looking at sine waves.
But then its single channel, uses a Xilinx FPGA and a Picmicro for USB transfer.
Single channel is an easy fix, add another ADC.
I personally work with altera CPLD's so i wont use a Xilinx device and i will use a CPLD and not a FPGA.
As a CPLD is a lot smaller then a FPGA i will need to have a separate SRAM IC for buffering.
Not a real problem, 64 or 128K ram is less then 5 euro's, even 10nS speed SRAM.
I never used a Picmicro for USB transfer, i only used 16F 8 bits Picmicro's until now.
I have used FTDI devices before, the normal FT232 but also the very fast FT2232H so USB transfer is not a problem.
I have some good experience with high speed analog design, tip for DP, even a 1pf capacity between the inputs of the ADC and the ground can be troublesome.
So removing a piece of the ground plane underneath the inputs of the ADC can help a lot for analog performance :)
All with all, in theory i should be able to make a scope, only the PC software is a bit hard for me.
The whole project will be open source so if someone else can help with the software it would be awesome.
Until now I only have design ideas on paper.
When my summer holiday starts I want to have a PCB design done so I can give Iteadstudio something to do :)
2 ADC's, ADS830@ 50Mhz
2 speedy op-amps, TI has some nice ones for a low price
1 SRAM Buffer, 64KByte, at least 10ns speed
1 CPLD, EPM570 from altera, fast enough and because the SRAM is a separate IC its is probably big enough.
A CPLD doesnâ€™t need a SRAM IC to load code from so CPLD + SRAM is a bit cheaper then an FPGA.
1 FT232 in bitbang mode for a max of 12Mbit USB transfer speed.
I could use a FT2232H but that one is double the price of a FT232
A better 5V and -5V power supply than the USB ones.
And thatch about it :)
well I need a buffer, 2 ADC's at 50Mhz create a 100MByte per sec dataflow and its madness to send that trough USB.
I normally get 10 to 12MByte with a FT2232H, 100Mbyte is USB3 range and roughly impossible to do as a student.
I will use a FT232R in bitbang mode, 4 I/O for data and 4 for handshaking/setting trigger/other stuff
at 12Mbit I will have ~750Kbyte per sec with 4 I/O ports.
With a 64K buffer it means I can send it trough USB more then 10 times per second.
Enough, not going to mess with that :)
but 64K buffer means 32K per channel.
At 50Mhz thatâ€™s just 640uS of data, seems really tiny right?
Now image you are looking at a 1Mhz sine-wave signal, one sine-wave is then 1uS
you can fit 640 whole sines in that buffer, more then enough it seems
now imagine looking at a 1Khz signal, thatâ€™s 1mS for one sine-wave
Now you can't even fit one sine-wave in the buffer, thatâ€™s bad!
The solution is simple, you can lower the speed of the ADC or lower the speed that the buffer saves the data.
Both solutions do the same, making the ADC run 100 times slower or just saving one in every 100 samples to the buffer, both ideas slow the whole thing down by 100 times.
When everything is slowed down 100 times you can fit 64mS in the 32K buffer, a lot better.
Then 1Khz isnâ€™t a problem anymore.
Like I said in the top of this slightly to long post, this wont be done in a month.
I want to have it done in begin august when school starts again.
The whole project will be open source and if it actually works and people want it I might poke seeedstudio about selling them.
Thatâ€™s it for today, when I have more info about anything related to this project I will make another massive post ;)
I will try to connect a ADS830 to a FT2232H directly next week, ADS @ 6 to 10Mhz so I donâ€™t need any form of a buffer and see what happens.
Ideas, please share them :)
I'll be really interested to see these parts of your project:
*Altera chip, I'd also like to port the Demon core to an Altera FPGA (not CPLD)
Keep us updated :)
well, i never used VHDL or Verilog, i use schematic entry mode >:)
i already made a fully working 4 bit ALU in Schematic entry mode so a scope is a new challenge.
with 570 logic cells i can add a fair amount of counters etc etc for SRAM control so i think it should work out fine.
i used the FT2232H before and i find it quite easy to use when i need lots of speed.
i made some documentation for school for it but i am afraid its in dutch, so posting it here wont be really helpful for most of you ;)
going to make a PCB for it tomorrow so i can connect an ADC to the FT2232H, parts will arrive monday i think.
Wij spreken nederlands hier :) Grtz.
Schematic entry will become quite bulky for this design. I designed a simple LA in verilog for a 72macrocell CPLD. It is fairly well documented here:
http://dangerousprototypes.com/docs/Lul ... c_analyzer (http://dangerousprototypes.com/docs/Lulu:_Yet_another_logic_analyzer)
Here are some useful links if you want to build your own scope:
- A nice HDL example (http://http://www.fpga4fun.com/digitalscope.html) of an oscilloscope using a FIFO and trigger
- A 100 MHz input stage (http://http://www.soudez.be/joomla/content/view/12/27/lang,en/)
- A firmware development/improvement (http://http://sourceforge.net/apps/trac/welecw2000a/) for the DSO "Welec 2000a- series"
- The (sad) story about the DSO Quad (http://http://garden.seeedstudio.com/index.php?title=DSO_Quad) portable scope (why (http://http://www.seeedstudio.com/forum/viewtopic.php?f=22&t=1944) sad?)
about your original scope with 1MSPS you can easily get 400KHZ spectrum out of it, by using software, search the net about fast furier transform, oversampeling, and digital filtering.
By defiiniton any signal that is sampled at a freq. Fs can be reproduced fully up to the freq Fm = Fs/2 by simply adding a low pass filter with a freq max at Fm. of course you have to add a input fillter as well that cuts of any freq higher then Fm.
once the signal has been sampled and is in your computer you can reproduce it on the screen using varius digital filtering tehniques and fft.
here is an explanation without the math of how it works.
when you sample a signas with a maximum freq Fm with a freq Fs = Fm*2, the spectrum of the resulting signal is a copyied spectrum of the original and pasted all over the infinit spectrum at Fs intervals.
you get a signal that has the original signal at 0->Fm, at Fs->Fs+Fm, 2Fs->2Fs+Fm............*well actualy there is a neg. component but lets not get into it as it is not important. so to retrive the original all you have to do is cutt off all the higher componets then Fm. the cool par is that all this can be simulated in a computer.
in other words a signa with a spectrum od 0->4KHZ sampled at 8Ksps can be fully recoverd on the output be it a DAC circuit or the screen of a monitor, all the information about hte signa is inside those samples, in other words the resolution at witch you can display it on a monitor can theroeticly be infinite!
-even thoug you only get 2 samples per cycle of the original signal, you can show on your screen 1000 samples, per cycle.
Fs=FM*2 is the theretical margin, but since input filters can never be perfect, and if any component above Fm get trough they will generate error in the resulting signal so it is easier to use Fs = 2.5 * Fm, and a cheaper filter with a lower slope.
-sorry if this was rant, but i thought all DSO and computer oscilator projects should know that they don't need 100 samples per cycle to show the signal properly on the screen. 3 is more then enough, 10 -15 is more then enough even for sqare waves!
PS. the input filter is a must, and in many ADC circuits the most expensive part of the circuit.
P.S.S that means that with a 50MSPS you can show 20 MHZ signals on your scope with ease.
full math and explanation can be fount at this sites
http://www2.tek.com/cmswpt/tidetails.lo ... 4295&lc=EN (http://www2.tek.com/cmswpt/tidetails.lotr?ct=TI&cs=Application+Note&ci=14295&lc=EN)
near the bottom under
How Sin(x)/x Interpolation Works
http://www.johnloomis.org/ece561/notes/ ... nterp.html (http://www.johnloomis.org/ece561/notes/sinc_interp/sinc_interp.html)
http://health.tau.ac.il/Communication%2 ... nting.html (http://health.tau.ac.il/Communication%20Disorders/noam/multirate/implementing/implementing.html)
of coure all this is in Spectrum, and since only sine wawe have a single spectrum defining them the above is the sine wave cut off point, square waves have many harmonics and to display it as square would require a lot of them, so the freq of a well shown square wave will be lower than that of the sine wave, about 7 times for 4 harmonics to be shown.
this is an image of a 4 harmonic square wave (http://http://www.techmind.org/dsp/fig2.gif)
got one ADS working :)
had some free time and made a small PCB with a ADS830 and a fast opamp.
it works, didnt test anything special, 8 digital I/O's to a logic analyzer.
so i know how to connect the while stuff, next week more free time to make a full PCB :)
will post a picture tomorrow
ADS830 with FT2232 is interesting. I can't wait to see where this goes.
BRC electronics is the name we use for our project group on school ;)
the PCB and soldering are ugly ugly ugly, we used the soldering over first but half the stuff didn't solder correctly so i redid every solder :(
this connects to my breadboard, from breadboard to FT2232 to PC.
6Mhz sample rate, actually works.
vb.net gets the data and puts it in a text file, text files goes in excel and i see some sine waves :)
I got a block diagram.
look at it.
from the input there's a amplifier that amplifies the input 10 times and a resistor divider to divide the input by 100.
all selectable so you can amplify the input by 10 or divide it by 10 or 100 or just keep it this way.
any ideas, please post them :)
party time, analog inputstage done in multisim:
in 2 weeks i will have a new scope, 4 * 250Mhz analog tek, then i can build the input stage and verify it in real life.
for now i have to do with a multisim simulation but it looks promising.
i will need some bad-ass opamps to reach 10+ Mhz so i used virtual ones for now.
the 10X amplifier will be an LT6200-10, to make it easy i used the specs of an LT6200-10 for all the virtual opamps.
the buffer wil be something like an AD8065 (really low input current and fairly fast), the one for the offset something like an LT1222 (fast enough)
time to enter it in eagle together with the ADS830 and stuff.
i think that i will make 2 PCB's
one for analog and one for digital, analog one will have everything from input to ADC and the digital one will have the CPLD and FT(2)232
hope to hear some feedback :)
Have you thought of using USB 3.0 instead of an on board memory chip?
USB 3.0 transievers are out there, and it should be able to easily transfer 200 msps at 8 bit values without any problem. Then you can store the data in RAM on the computer instead of the HDD by allocating say, a few Megabytes with malloc or something of the sort. No need to worry about storage capacity, since the limit is how much ram you have.
Just a thought there though, I never looked much more into it.
http://www.mouser.com/ProductDetail/Tex ... BVE2NM8%3d (http://www.mouser.com/ProductDetail/Texas-Instruments/TUSB1310ZAY/?qs=sGAEpiMZZMtOXy69nW9rM1KODuQjDGj0Xu%2fBBVE2NM8%3d) <-- ah there we go.
The board would obviously have to be at least a 4 layer board to accompany the 175pin BGA though.
USB2 is high speed enough for me :)
the added price of a RAM IC is much much lower then a USB3.0 IC and 4 layer board.
and USB3 looks a lot harder then just using a FT2232, FTDI has drivers available and i already worked with a FT2232 before.
the FT2232 easily gets 10+ Mbyte per second, thats more then enough with 64K 16 bit RAM, tjhats just 128Kbyte of data.
I wonder how much bandwidth can you get, sampling in real time, with the ADC connected directly to the FT2232, with a simple program displaying the info on the computer side...
since I dont have a real scope and I dont know how to program an CPLD or FPGA it would be a great project to me :D
i had a testsetup like that, got me 6Msps of data, roughly 500Khz without Sin(x)/x Interpolation.
with Sin(x)/x Interpolation 2Mhz should be possible.
the downside is, as soon as you plug in an USb stick or external HDD and start copying things the bandwith from the FT2232 plummits.
USB printer and printing a big file does the same.
that's no problem at all, I'll keep in mind not to plug anything while the scope is working
can you share the schematic and program?
my program is semi-working, it captures 1 second of data and opens that in excel.
its not a real scope and its rather buggy.
so i recommend you to write you're own program for it.
i have 2 PCB's, i got a PCB for the FT2232 board from FTDI and a PCB with the ADC.
warning, i used an 741 opamp in there, i was not sure what opamp was needed so its a placeholder.
replace with any fast opamp (20Mhz+)
and the PCB's are a total mess, there pure test PCB's, USE AT OWN RISK.
And i am a bit further, got a schematic of the full inputstage, so inputstage + ADC's
warning, picture is BIG:
PCB with CPLD and memory will take care of all power supply's.
the opamps will be the LT6200, LT6200-10 and probably an AD8065.
after a little thinking i decided to drop the FT2232H for the FT232R.
the FT232R can get 3Mbaud, ~300Kbyte per sec while still using the easy virtual com port.
for the buffer, even 4Kbyte per channel is enough.
with 4Kbyte of buffer and 50MSPS sampling we get:
4Kbyte / 50MSPS = 80 uS sampling time.
looking at 20Mhz you can save 80uS / 50nS = 1600 sine waves in the buffer!
at 2Mhz its still 160 and at 200Khz you can fit 16 sine waves in it.
and its always possible to divide the sampling speed, heck, else the CPLD gets bored.
with a 4Kbyte buffer and 300Kbyte/Sec speed you can update the screen 300KB per Sec /4Kbyte * 2 channels = 37,5 times a second.
thats plenty :D
the FT232 is cheaper, doesn't need the eeprom and crystal and all other parts that the FT2232H needs.
the opamps are expensive enough.
schematic for CPLD board should be done tomorrow.
If you want time base accuracy you still might want to use an XTAL. The internal oscillator will be very temperature sensitive. You cannot beat the phase noise of a high Q mechanical oscillator.
a small update, first schematic of the CPLD board.
there are some obvious flaws, no transistor to switch the relays, no AGND.
next time i want to have the PCB's done and schematics updated :)